soc/interconnect/axi: add connect methods for convenience
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78a631f392
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@ -55,6 +55,23 @@ def r_description(data_width, id_width):
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("id", id_width)
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("id", id_width)
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]
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]
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def _connect_axi(master, slave):
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channel_modes = {
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"aw": "master",
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"w" : "master",
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"b" : "slave",
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"ar": "master",
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"r" : "slave",
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}
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r = []
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for channel, mode in channel_modes.items():
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if mode == "master":
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m, s = getattr(master, channel), getattr(slave, channel)
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else:
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s, m = getattr(master, channel), getattr(slave, channel)
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r.extend(m.connect(s))
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return r
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class AXIInterface:
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class AXIInterface:
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def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys"):
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def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys"):
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self.data_width = data_width
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self.data_width = data_width
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@ -68,6 +85,9 @@ class AXIInterface:
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self.ar = stream.Endpoint(ax_description(address_width, id_width))
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self.ar = stream.Endpoint(ax_description(address_width, id_width))
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self.r = stream.Endpoint(r_description(data_width, id_width))
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self.r = stream.Endpoint(r_description(data_width, id_width))
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def connect(self, slave):
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return _connect_axi(self, slave)
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# AXI Lite Definition ------------------------------------------------------------------------------
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# AXI Lite Definition ------------------------------------------------------------------------------
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def ax_lite_description(address_width):
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def ax_lite_description(address_width):
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@ -138,6 +158,9 @@ class AXILiteInterface:
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r.append(pad.eq(sig))
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r.append(pad.eq(sig))
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return r
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return r
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def connect(self, slave):
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return _connect_axi(self, slave)
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def write(self, addr, data, strb=None):
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def write(self, addr, data, strb=None):
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if strb is None:
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if strb is None:
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strb = 2**len(self.w.strb) - 1
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strb = 2**len(self.w.strb) - 1
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