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Merge pull request #421 from betrusted-io/clk0_fractional 

add fractional division options to clk0 config on PLL
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enjoy-digital 2020-03-13 14:15:24 +01:00 committed by GitHub
parent eb9f54b2bc 5b92bf2d57
commit f34593a17d
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1 changed files with 14 additions and 0 deletions
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14
litex/soc/cores/clock.py
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@ -53,6 +53,7 @@ def compute_config_log(logger, config):
class XilinxClocking(Module, AutoCSR):
clkfbout_mult_frange = (2, 64+1)
clkout_divide_range = (1, 128+1)
clkout0_divide_range = (2, (128+0.125), 0.125)
def __init__(self, vco_margin=0):
self.vco_margin = vco_margin
@ -122,6 +123,19 @@ class XilinxClocking(Module, AutoCSR):
config["clkout{}_phase".format(n)] = p
valid = True
break
if not valid and n == 0:
# clkout0 supports fractional division, try the fractional range as a fallback
(start, stop, step) = self.clkout0_divide_range
d = start
while d < stop:
clk_freq = vco_freq / d
if abs(clk_freq - f) <= f * m:
config["clkout{}_freq".format(n)] = clk_freq
config["clkout{}_divide".format(n)] = d
config["clkout{}_phase".format(n)] = p
valid = True
break
d += step
if not valid:
all_valid = False
else: