Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

README: cleanup

Browse source
This commit is contained in:
Florent Kermarrec 2018-02-23 14:15:41 +01:00
parent fb088b79dd
commit f372e8c880
1 changed files with 7 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
README
View file

@ -11,7 +11,11 @@
--------
LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
our cores, integrate them in complete SoC and load/flash them to the hardware
and experiment new features.
and experiment new features. (structure is kept close to MiSoC to ease
collaboration)
Typical LiteX design flow:
--------------------------
+---------------+
|FPGA toolchains|
@ -26,15 +30,12 @@ and experiment new features.
+----------------------+ | |
|LiteX Cores Ecosystem +--> |
+----------------------+ +-^-------^-+
(Eth,,SATA,,DRAM,,USB, | |
(Eth, SATA, DRAM, USB, | |
PCIe, Video, etc...) + +
board target
file file
The structure of LiteX is kept close to MiSoC to ease collaboration between
projects.
[> Sub-packages
---------------
gen: