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fhdl/verilog: initialize internal read-only signals with their reset values

This commit is contained in:
Sebastien Bourdeauducq 2012-04-01 16:39:11 +02:00
parent 0dfc215fe8
commit f3ae22f488
1 changed files with 11 additions and 0 deletions
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11
migen/fhdl/verilog.py
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@ -220,6 +220,16 @@ def _printmemories(f, ns, handler, clk):
r += handler(memory, ns, clk) r += handler(memory, ns, clk)
return r return r
def _printinit(f, exclude, ns):
r = ""
signals = list_signals(f) - exclude - list_targets(f)
if signals:
r += "initial begin\n"
for s in signals:
r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset) + ";\n"
r += "end\n\n"
return r
def convert(f, ios=set(), name="top", def convert(f, ios=set(), name="top",
clk_signal=None, rst_signal=None, clk_signal=None, rst_signal=None,
return_ns=False, return_ns=False,
@ -243,6 +253,7 @@ def convert(f, ios=set(), name="top",
r += _printsync(f, ns, clk_signal, rst_signal) r += _printsync(f, ns, clk_signal, rst_signal)
r += _printinstances(f, ns, clk_signal, rst_signal) r += _printinstances(f, ns, clk_signal, rst_signal)
r += _printmemories(f, ns, memory_handler, clk_signal) r += _printmemories(f, ns, memory_handler, clk_signal)
r += _printinit(f, ios, ns)
r += "endmodule\n" r += "endmodule\n"
if return_ns: if return_ns: