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global: pep8 (E225)

This commit is contained in:
Florent Kermarrec 2015-04-13 17:01:05 +02:00
parent 042b160b81
commit f3c010c1d5
4 changed files with 8 additions and 8 deletions
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6
misoclib/com/spi/__init__.py
View File

@ -48,9 +48,9 @@ class SPIMaster(Module, AutoCSR):
) )
] ]
self.comb +=[ self.comb += [
set_clk.eq(i==div//2-1), set_clk.eq(i == (div//2-1)),
clr_clk.eq(i==div-1) clr_clk.eq(i == (div-1))
] ]
# fsm # fsm

4
misoclib/mem/sdram/phy/initsequence.py
View File

@ -31,7 +31,7 @@ static void command_p{n}(int cmd)
#define command_prd(X) command_p{rdphase}(X) #define command_prd(X) command_p{rdphase}(X)
#define command_pwr(X) command_p{wrphase}(X) #define command_pwr(X) command_p{wrphase}(X)
""".format(rdphase=str(sdram_phy_settings.rdphase), wrphase=str(sdram_phy_settings.wrphase)) """.format(rdphase=str(sdram_phy_settings.rdphase), wrphase=str(sdram_phy_settings.wrphase))
r +="\n" r += "\n"
# #
# sdrrd/sdrwr functions utilities # sdrrd/sdrwr functions utilities
@ -54,7 +54,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
{sdram_dfii_pix_rddata_addr} {sdram_dfii_pix_rddata_addr}
}}; }};
""".format(n=nphases, sdram_dfii_pix_rddata_addr=",\n\t".join(sdram_dfii_pix_rddata_addr)) """.format(n=nphases, sdram_dfii_pix_rddata_addr=",\n\t".join(sdram_dfii_pix_rddata_addr))
r +="\n" r += "\n"
# init sequence # init sequence
cmds = { cmds = {

2
misoclib/mem/sdram/phy/s6ddrphy.py
View File

@ -87,7 +87,7 @@ class S6DDRPHY(Module):
# register dfi cmds on half_rate clk # register dfi cmds on half_rate clk
r_dfi = Array(Record(phase_cmd_description(addressbits, bankbits)) for i in range(nphases)) r_dfi = Array(Record(phase_cmd_description(addressbits, bankbits)) for i in range(nphases))
for n, phase in enumerate(self.dfi.phases): for n, phase in enumerate(self.dfi.phases):
sd_sdram_half +=[ sd_sdram_half += [
r_dfi[n].address.eq(phase.address), r_dfi[n].address.eq(phase.address),
r_dfi[n].bank.eq(phase.bank), r_dfi[n].bank.eq(phase.bank),
r_dfi[n].cs_n.eq(phase.cs_n), r_dfi[n].cs_n.eq(phase.cs_n),

4
misoclib/soc/sdram.py
View File

@ -39,8 +39,8 @@ class SDRAMSoC(SoC):
dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2 dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
sdram_width = phy.settings.dfi_databits//dfi_databits_divisor sdram_width = phy.settings.dfi_databits//dfi_databits_divisor
main_ram_size = 2**(phy.module.geom_settings.bankbits+ main_ram_size = 2**(phy.module.geom_settings.bankbits +
phy.module.geom_settings.rowbits+ phy.module.geom_settings.rowbits +
phy.module.geom_settings.colbits)*sdram_width//8 phy.module.geom_settings.colbits)*sdram_width//8
# XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories. # XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories.
main_ram_size = min(main_ram_size, 256*1024*1024) main_ram_size = min(main_ram_size, 256*1024*1024)