soc/SoCBusHandler: Add io_regions_check attribute and and disable IO region check with CPUNone.
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@ -144,14 +144,15 @@ class SoCBusHandler(Module):
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raise SoCError()
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raise SoCError()
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# Create Bus
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# Create Bus
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self.standard = standard
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self.standard = standard
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self.data_width = data_width
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self.data_width = data_width
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self.address_width = address_width
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self.address_width = address_width
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self.masters = {}
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self.masters = {}
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self.slaves = {}
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self.slaves = {}
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self.regions = {}
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self.regions = {}
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self.io_regions = {}
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self.io_regions = {}
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self.timeout = timeout
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self.io_regions_check = True
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self.timeout = timeout
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self.logger.info("{}-bit {} Bus, {}GiB Address Space.".format(
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self.logger.info("{}-bit {} Bus, {}GiB Address Space.".format(
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colorer(data_width), colorer(standard), colorer(2**address_width/2**30)))
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colorer(data_width), colorer(standard), colorer(2**address_width/2**30)))
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@ -197,22 +198,23 @@ class SoCBusHandler(Module):
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self.regions[name] = region
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self.regions[name] = region
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# Else add Region.
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# Else add Region.
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else:
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else:
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if self.check_region_is_io(region):
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if self.io_regions_check:
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# If Region is an IO Region it is not cached.
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if self.check_region_is_io(region):
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if region.cached:
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# If Region is an IO Region it is not cached.
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self.logger.error("{} {}".format(
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if region.cached:
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colorer(name + " Region in IO region, it can't be cached:", color="red"),
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self.logger.error("{} {}".format(
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str(region)))
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colorer(name + " Region in IO region, it can't be cached:", color="red"),
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self.logger.error(self)
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str(region)))
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raise SoCError()
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self.logger.error(self)
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else:
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raise SoCError()
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# If Region is not an IO Region it is cached.
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else:
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if not region.cached:
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# If Region is not an IO Region it is cached.
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self.logger.error("{} {}".format(
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if not region.cached:
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colorer(name + " Region not in IO region, it must be cached:", color="red"),
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self.logger.error("{} {}".format(
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str(region)))
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colorer(name + " Region not in IO region, it must be cached:", color="red"),
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self.logger.error(self)
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str(region)))
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raise SoCError()
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self.logger.error(self)
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raise SoCError()
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self.regions[name] = region
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self.regions[name] = region
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# Check for overlap with others IO regions.
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# Check for overlap with others IO regions.
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overlap = self.check_regions_overlap(self.regions)
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overlap = self.check_regions_overlap(self.regions)
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@ -919,6 +921,8 @@ class SoC(Module):
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if isinstance(self.cpu, cpu.CPUNone):
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if isinstance(self.cpu, cpu.CPUNone):
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# With CPUNone, give priority to User's mapping.
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# With CPUNone, give priority to User's mapping.
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self.mem_map = {**self.cpu.mem_map, **self.mem_map}
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self.mem_map = {**self.cpu.mem_map, **self.mem_map}
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# With CPUNone, disable IO regions check.
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self.bus.io_regions_check = False
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else:
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else:
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# Override User's mapping with CPU constrainted mapping (and warn User).
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# Override User's mapping with CPU constrainted mapping (and warn User).
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for n, origin in self.cpu.mem_map.items():
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for n, origin in self.cpu.mem_map.items():
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