Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fhdl/structure/Memory: fix we width

This commit is contained in:
Sebastien Bourdeauducq 2012-11-23 19:21:52 +01:00
parent 784a399431
commit f42683b71e
1 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
migen/fhdl/structure.py
View File

@ -338,7 +338,10 @@ class Memory(HUID):
adr = Signal(BV(bits_for(self.depth-1))) adr = Signal(BV(bits_for(self.depth-1)))
dat_r = Signal(BV(self.width)) dat_r = Signal(BV(self.width))
if write_capable: if write_capable:
we = Signal() if we_granularity:
we = Signal(BV(self.width//we_granularity))
else:
we = Signal()
dat_w = Signal(BV(self.width)) dat_w = Signal(BV(self.width))
else: else:
we = None we = None
@ -348,8 +351,8 @@ class Memory(HUID):
else: else:
re = None re = None
mp = MemoryPort(adr, dat_r, we, dat_w, mp = MemoryPort(adr, dat_r, we, dat_w,
async_read, re, we_granularity, mode, async_read, re, we_granularity, mode,
clock_domain) clock_domain)
self.ports.append(mp) self.ports.append(mp)
return mp return mp