fhdl/structure/Memory: fix we width

2012-11-23 19:21:52 +01:00 · 2012-11-23 19:21:52 +01:00 · f42683b71e
parent 784a399431
commit f42683b71e
1 changed files with 6 additions and 3 deletions
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@ -338,6 +338,9 @@ class Memory(HUID):
 		adr = Signal(BV(bits_for(self.depth-1)))
 		dat_r = Signal(BV(self.width))
 		if write_capable:
+			if we_granularity:
+				we = Signal(BV(self.width//we_granularity))
+			else:
 				we = Signal()
 			dat_w = Signal(BV(self.width))
 		else: