soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined
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@ -53,6 +53,8 @@ class SDRAMSoC(SoC):
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# XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories.
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# XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories.
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main_ram_size = min(main_ram_size, 256*1024*1024)
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main_ram_size = min(main_ram_size, 256*1024*1024)
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l2_size = self.sdram_controller_settings.l2_size
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l2_size = self.sdram_controller_settings.l2_size
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if l2_size:
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self.add_constant("L2_SIZE", l2_size)
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# add a Wishbone interface to the DRAM
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# add a Wishbone interface to the DRAM
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wb_sdram = wishbone.Interface()
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wb_sdram = wishbone.Interface()
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@ -355,7 +355,10 @@ static void do_command(char *c)
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else if(strcmp(token, "mw") == 0) mw(get_token(&c), get_token(&c), get_token(&c));
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else if(strcmp(token, "mw") == 0) mw(get_token(&c), get_token(&c), get_token(&c));
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else if(strcmp(token, "mc") == 0) mc(get_token(&c), get_token(&c), get_token(&c));
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else if(strcmp(token, "mc") == 0) mc(get_token(&c), get_token(&c), get_token(&c));
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else if(strcmp(token, "crc") == 0) crc(get_token(&c), get_token(&c));
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else if(strcmp(token, "crc") == 0) crc(get_token(&c), get_token(&c));
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#ifdef L2_SIZE
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else if(strcmp(token, "flushl2") == 0) flush_l2_cache();
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else if(strcmp(token, "flushl2") == 0) flush_l2_cache();
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#endif
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#ifdef FLASH_BOOT_ADDRESS
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#ifdef FLASH_BOOT_ADDRESS
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else if(strcmp(token, "flashboot") == 0) flashboot();
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else if(strcmp(token, "flashboot") == 0) flashboot();
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@ -67,16 +67,14 @@ void flush_cpu_dcache(void)
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#endif
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#endif
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}
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}
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#ifdef CSR_L2_CACHE_BASE
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#ifdef L2_SIZE
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void flush_l2_cache(void)
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void flush_l2_cache(void)
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{
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{
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unsigned int l2_nwords;
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unsigned int i;
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unsigned int i;
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register unsigned int addr;
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register unsigned int addr;
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register unsigned int dummy;
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register unsigned int dummy;
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l2_nwords = 1 << l2_cache_size_read();
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for(i=0;i<2*L2_SIZE;i++) {
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for(i=0;i<2*l2_nwords;i++) {
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addr = MAIN_RAM_BASE + i*4;
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addr = MAIN_RAM_BASE + i*4;
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#if defined (__lm32__)
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#if defined (__lm32__)
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__asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
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__asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
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@ -87,8 +85,4 @@ void flush_l2_cache(void)
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#endif
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#endif
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}
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}
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}
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}
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#else
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void flush_l2_cache(void)
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{
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}
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#endif
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#endif
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