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Merge pull request #200 from gsomlo/gls-rocket-variants 

cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants
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enjoy-digital 2019-06-18 13:15:30 +02:00 committed by GitHub
parent c0df9e0823 f75863fc31
commit f47b4902e5
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1 changed files with 12 additions and 6 deletions
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18
litex/soc/cores/cpu/rocket/core.py
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@ -36,10 +36,16 @@ from migen import *
from litex.soc.interconnect import axi from litex.soc.interconnect import axi
from litex.soc.interconnect import wishbone from litex.soc.interconnect import wishbone
CPU_VARIANTS = ["standard"] CPU_VARIANTS = {
"standard": "freechips.rocketchip.system.LitexConfig",
"linux": "freechips.rocketchip.system.LitexLinuxConfig",
"full": "freechips.rocketchip.system.LitexFullConfig",
}
GCC_FLAGS = { GCC_FLAGS = {
"standard": "-march=rv64imac -mabi=lp64 ", "standard": "-march=rv64imac -mabi=lp64 ",
"linux": "-march=rv64imac -mabi=lp64 ",
"full": "-march=rv64imafdc -mabi=lp64 ",
} }
class RocketRV64(Module): class RocketRV64(Module):
@ -223,16 +229,16 @@ class RocketRV64(Module):
self.submodules += mem_a2w, mem_dc, mmio_a2w, mmio_dc self.submodules += mem_a2w, mem_dc, mmio_a2w, mmio_dc
# add verilog sources # add verilog sources
self.add_sources(platform) self.add_sources(platform, variant)
@staticmethod @staticmethod
def add_sources(platform): def add_sources(platform, variant="standard"):
vdir = os.path.join( vdir = os.path.join(
os.path.abspath(os.path.dirname(__file__)), "verilog") os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_sources( platform.add_sources(
os.path.join(vdir, "generated-src"), os.path.join(vdir, "generated-src"),
"freechips.rocketchip.system.LitexConfig.v", CPU_VARIANTS[variant] + ".v",
"freechips.rocketchip.system.LitexConfig.behav_srams.v", CPU_VARIANTS[variant] + ".behav_srams.v",
) )
platform.add_sources( platform.add_sources(
os.path.join(vdir, "vsrc"), os.path.join(vdir, "vsrc"),