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examples: remove outdated wb_intercon simulation

This commit is contained in:
Sebastien Bourdeauducq 2012-03-08 18:17:56 +01:00
parent 84aa703447
commit f4adb0fe9c
5 changed files with 0 additions and 397 deletions
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20
examples/wb_intercon/Makefile
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SOURCES=tb_intercon.v intercon.v master.v slave.v
all: tb_intercon
sim: tb_intercon
./tb_intercon
cversim: $(SOURCES)
cver $(SOURCES)
clean:
rm -f tb_intercon intercon.v intercon.vcd verilog.log
tb_intercon: $(SOURCES)
iverilog -o tb_intercon $(SOURCES)
intercon.v: intercon_conv.py
python3 intercon_conv.py > intercon.v
.PHONY: clean sim cversim

19
examples/wb_intercon/intercon_conv.py
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from migen.fhdl import verilog
from migen.bus import wishbone
m1 = wishbone.Interface()
m2 = wishbone.Interface()
s1 = wishbone.Interface()
s2 = wishbone.Interface()
wishbonecon0 = wishbone.InterconnectShared(
[m1, m2],
[(0, s1), (1, s2)],
register=True,
offset=1)
frag = wishbonecon0.get_fragment()
v = verilog.convert(frag, name="intercon", ios={m1.cyc, m1.stb, m1.we, m1.adr, m1.sel, m1.dat_w, m1.dat_r, m1.ack,
m2.cyc, m2.stb, m2.we, m2.adr, m2.sel, m2.dat_r, m2.dat_w, m2.ack,
s1.cyc, s1.stb, s1.we, s1.adr, s1.sel, s1.dat_r, s1.dat_w, s1.ack,
s2.cyc, s2.stb, s2.we, s2.adr, s2.sel, s2.dat_r, s2.dat_w, s2.ack})
print(v)

89
examples/wb_intercon/master.v
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/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module master #(
parameter id = 0,
parameter nreads = 10,
parameter nwrites = 10,
parameter p = 4
) (
input sys_clk,
input sys_rst,
output reg [31:0] dat_w,
input [31:0] dat_r,
output reg [29:0] adr,
output reg we,
output reg [3:0] sel,
output cyc,
output stb,
input ack,
output reg tend
);
integer rcounter;
integer wcounter;
reg active;
assign cyc = active;
assign stb = active;
always @(posedge sys_clk) begin
if(sys_rst) begin
dat_w <= 0;
adr <= 0;
we <= 0;
sel <= 0;
active <= 0;
rcounter = 0;
wcounter = 0;
tend <= 0;
end else begin
if(ack) begin
if(~active)
$display("[M%d] Spurious ack", id);
else begin
if(we)
$display("[M%d] Ack W: %x:%x [%x]", id, adr, dat_w, sel);
else
$display("[M%d] Ack R: %x:%x [%x]", id, adr, dat_r, sel);
end
active <= 1'b0;
end else if(~active) begin
if(($random % p) == 0) begin
adr <= (($random % 5) << (30-2)) + id;
sel <= sel + 1;
active <= 1'b1;
if(($random % 2) == 0) begin
/* Read */
we <= 1'b0;
rcounter = rcounter + 1;
end else begin
/* Write */
we <= 1'b1;
dat_w <= ($random << 16) + id;
wcounter = wcounter + 1;
end
end
end
tend <= (rcounter >= nreads) && (wcounter >= nwrites);
end
end
endmodule

55
examples/wb_intercon/slave.v
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/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module slave #(
parameter id = 0,
parameter p = 3
) (
input sys_clk,
input sys_rst,
input [31:0] dat_w,
output reg [31:0] dat_r,
input [29:0] adr,
input we,
input [3:0] sel,
input cyc,
input stb,
output reg ack
);
always @(posedge sys_clk) begin
if(sys_rst) begin
dat_r <= 0;
ack <= 0;
end else begin
if(cyc & stb & ~ack) begin
if(($random % p) == 0) begin
ack <= 1;
if(~we)
dat_r <= ($random << 16) + id;
if(we)
$display("[S%d] Ack W: %x:%x [%x]", id, adr, dat_w, sel);
else
$display("[S%d] Ack R: %x:%x [%x]", id, adr, dat_r, sel);
end
end else
ack <= 0;
end
end
endmodule

214
examples/wb_intercon/tb_intercon.v
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/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2011, 2012 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_conbus();
reg sys_rst;
reg sys_clk;
//------------------------------------------------------------------
// Wishbone master wires
//------------------------------------------------------------------
wire [29:0] m1_wishbone_adr,
m2_wishbone_adr;
wire [31:0] m1_wishbone_dat_r,
m1_wishbone_dat_w,
m2_wishbone_dat_r,
m2_wishbone_dat_w;
wire [3:0] m1_wishbone_sel,
m2_wishbone_sel;
wire m1_wishbone_we,
m2_wishbone_we;
wire m1_wishbone_cyc,
m2_wishbone_cyc;
wire m1_wishbone_stb,
m2_wishbone_stb;
wire m1_wishbone_ack,
m2_wishbone_ack;
//------------------------------------------------------------------
// Wishbone slave wires
//------------------------------------------------------------------
wire [29:0] s1_wishbone_adr,
s2_wishbone_adr;
wire [31:0] s1_wishbone_dat_r,
s1_wishbone_dat_w,
s2_wishbone_dat_r,
s2_wishbone_dat_w;
wire [3:0] s1_wishbone_sel,
s2_wishbone_sel;
wire s1_wishbone_we,
s2_wishbone_we;
wire s1_wishbone_cyc,
s2_wishbone_cyc;
wire s1_wishbone_stb,
s2_wishbone_stb;
wire s1_wishbone_ack,
s2_wishbone_ack;
//---------------------------------------------------------------------------
// Wishbone switch
//---------------------------------------------------------------------------
intercon dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
// Master 0
.m1_wishbone_dat_w(m1_wishbone_dat_w),
.m1_wishbone_dat_r(m1_wishbone_dat_r),
.m1_wishbone_adr(m1_wishbone_adr),
.m1_wishbone_we(m1_wishbone_we),
.m1_wishbone_sel(m1_wishbone_sel),
.m1_wishbone_cyc(m1_wishbone_cyc),
.m1_wishbone_stb(m1_wishbone_stb),
.m1_wishbone_ack(m1_wishbone_ack),
// Master 1
.m2_wishbone_dat_w(m2_wishbone_dat_w),
.m2_wishbone_dat_r(m2_wishbone_dat_r),
.m2_wishbone_adr(m2_wishbone_adr),
.m2_wishbone_we(m2_wishbone_we),
.m2_wishbone_sel(m2_wishbone_sel),
.m2_wishbone_cyc(m2_wishbone_cyc),
.m2_wishbone_stb(m2_wishbone_stb),
.m2_wishbone_ack(m2_wishbone_ack),
// Slave 0
.s1_wishbone_dat_r(s1_wishbone_dat_r),
.s1_wishbone_dat_w(s1_wishbone_dat_w),
.s1_wishbone_adr(s1_wishbone_adr),
.s1_wishbone_sel(s1_wishbone_sel),
.s1_wishbone_we(s1_wishbone_we),
.s1_wishbone_cyc(s1_wishbone_cyc),
.s1_wishbone_stb(s1_wishbone_stb),
.s1_wishbone_ack(s1_wishbone_ack),
// Slave 1
.s2_wishbone_dat_r(s2_wishbone_dat_r),
.s2_wishbone_dat_w(s2_wishbone_dat_w),
.s2_wishbone_adr(s2_wishbone_adr),
.s2_wishbone_sel(s2_wishbone_sel),
.s2_wishbone_we(s2_wishbone_we),
.s2_wishbone_cyc(s2_wishbone_cyc),
.s2_wishbone_stb(s2_wishbone_stb),
.s2_wishbone_ack(s2_wishbone_ack)
);
//---------------------------------------------------------------------------
// Masters
//---------------------------------------------------------------------------
wire m1_wishbone_end;
master #(
.id(0)
) m0 (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.dat_w(m1_wishbone_dat_w),
.dat_r(m1_wishbone_dat_r),
.adr(m1_wishbone_adr),
.we(m1_wishbone_we),
.sel(m1_wishbone_sel),
.cyc(m1_wishbone_cyc),
.stb(m1_wishbone_stb),
.ack(m1_wishbone_ack),
.tend(m1_wishbone_end)
);
wire m2_wishbone_end;
master #(
.id(1)
) m1 (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.dat_w(m2_wishbone_dat_w),
.dat_r(m2_wishbone_dat_r),
.adr(m2_wishbone_adr),
.we(m2_wishbone_we),
.sel(m2_wishbone_sel),
.cyc(m2_wishbone_cyc),
.stb(m2_wishbone_stb),
.ack(m2_wishbone_ack),
.tend(m2_wishbone_end)
);
//---------------------------------------------------------------------------
// Slaves
//---------------------------------------------------------------------------
slave #(
.id(0)
) s0 (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.dat_w(s1_wishbone_dat_w),
.dat_r(s1_wishbone_dat_r),
.adr(s1_wishbone_adr),
.we(s1_wishbone_we),
.sel(s1_wishbone_sel),
.cyc(s1_wishbone_cyc),
.stb(s1_wishbone_stb),
.ack(s1_wishbone_ack)
);
slave #(
.id(1)
) s1 (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.dat_w(s2_wishbone_dat_w),
.dat_r(s2_wishbone_dat_r),
.adr(s2_wishbone_adr),
.we(s2_wishbone_we),
.sel(s2_wishbone_sel),
.cyc(s2_wishbone_cyc),
.stb(s2_wishbone_stb),
.ack(s2_wishbone_ack)
);
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
wire all_end = m1_wishbone_end & m2_wishbone_end;
always begin
$dumpfile("intercon.vcd");
$dumpvars(1, dut);
sys_rst = 1'b1;
@(posedge sys_clk);
#1 sys_rst = 1'b0;
@(posedge all_end);
$finish;
end
endmodule