gensdrphy: fix dm generation
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@ -72,7 +72,11 @@ class GENSDRPHY(Module):
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drive_dq = Signal()
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self.sync += sd_dq_out.eq(self.dfi.p0.wrdata),
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self.specials += Tristate(pads.dq, sd_dq_out, drive_dq)
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self.sync += pads.dm.eq(~self.dfi.p0.wrdata_mask)
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self.sync += If(self.dfi.p0.wrdata_en,
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pads.dm.eq(self.dfi.p0.wrdata_mask)
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).Else(
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pads.dm.eq(0)
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)
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sd_dq_in_ps = Signal(d)
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self.sync.sys_ps += sd_dq_in_ps.eq(pads.dq)
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self.sync += self.dfi.p0.rddata.eq(sd_dq_in_ps)
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