gen/sim: hack to update vcd output file during simulation (allow visualizing progress directly and having a vcd file even when simulation fails or doesn't stop)

litex/gen/sim/core.py

@@ -279,6 +279,7 @@ class Simulator:
                     signals.add(cd.rst)
             for memory_array in mta.replacements.values():
                 signals |= set(memory_array)
+            self.vcd.init(signals)
             for signal in sorted(signals, key=lambda x: x.duid):
                 self.vcd.set(signal, signal.reset.value)
 

litex/gen/sim/vcd.py

@@ -21,8 +21,7 @@ def vcd_codes():
 class VCDWriter:
     def __init__(self, filename):
         self.filename = filename
-        self.buffer_file = tempfile.TemporaryFile(
-            dir=os.path.dirname(filename), mode="w+")
+        self.out_file = open(self.filename, "w")
         self.codegen = vcd_codes()
         self.codes = OrderedDict()
         self.signal_values = dict()
@@ -36,26 +35,20 @@ class VCDWriter:
             fmtstr = "b{:0" + str(l) + "b} {}\n"
         else:
             fmtstr = "{}{}\n"
+        code = self.codes[signal]
+        f.write(fmtstr.format(value, code))
+
+    def init(self, signals):
+        # generate codes
+        for signal in signals:
             try:
                 code = self.codes[signal]
             except KeyError:
                 code = next(self.codegen)
                 self.codes[signal] = code
-        f.write(fmtstr.format(value, code))
 
-    def set(self, signal, value):
-        if (signal not in self.signal_values
-                or self.signal_values[signal] != value):
-            self._write_value(self.buffer_file, signal, value)
-            self.signal_values[signal] = value
-
-    def delay(self, delay):
-        self.t += delay
-        self.buffer_file.write("#{}\n".format(self.t))
-
-    def close(self):
-        out = open(self.filename, "w")
-        try:
+        # write vcd header
+        out = self.out_file
         ns = build_namespace(self.codes.keys())
         for signal, code in self.codes.items():
             name = ns.get_name(signal)
@@ -67,14 +60,24 @@ class VCDWriter:
         out.write("$end\n")
         out.write("#0\n")
 
-            self.buffer_file.seek(0)
-            shutil.copyfileobj(self.buffer_file, out)
-            self.buffer_file.close()
-        finally:
-            out.close()
+    def set(self, signal, value):
+        if (signal not in self.signal_values
+                or self.signal_values[signal] != value):
+            self._write_value(self.out_file, signal, value)
+            self.signal_values[signal] = value
+
+    def delay(self, delay):
+        self.t += delay
+        self.out_file.write("#{}\n".format(self.t))
+
+    def close(self):
+        self.out_file.close()
 
 
 class DummyVCDWriter:
+    def init(self):
+        pass
+
     def set(self, signal, value):
         pass