Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

cpu/naxriscv fix xlen not being hashed, improve RV64 performances

Browse source
This commit is contained in:
Dolu1990 2022-03-18 15:39:58 +01:00
parent 58549834ec
commit f565bec7f1
1 changed files with 3 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
litex/soc/cores/cpu/naxriscv/core.py
View file

@ -184,6 +184,7 @@ class NaxRiscv(CPU):
def generate_netlist_name(reset_address):
md5_hash = hashlib.md5()
md5_hash.update(str(reset_address).encode('utf-8'))
md5_hash.update(str(NaxRiscv.xlen).encode('utf-8'))
for file in NaxRiscv.scala_paths:
a_file = open(file, "rb")
content = a_file.read()
@ -213,8 +214,8 @@ class NaxRiscv(CPU):
ndir = os.path.join(vdir, "ext", "NaxRiscv")
sdir = os.path.join(vdir, "ext", "SpinalHDL")
NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "52e6a5a1")
NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "d6ba3b6d")
NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "67389bd0")
NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "62531c60")
gen_args = []
gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")