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soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)

This commit is contained in:
Florent Kermarrec 2015-03-01 18:25:47 +01:00
parent 4f37d29d05
commit f58394f6af
3 changed files with 19 additions and 11 deletions
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16
misoclib/com/uart/__init__.py
View File

@ -15,16 +15,16 @@ class UART(Module, AutoCSR):
### ###
self.sync += [ self.sync += [
If(self._rxtx.re, If(self._rxtx.re,
phy.tx.sink.stb.eq(1), phy.sink.stb.eq(1),
phy.tx.sink.data.eq(self._rxtx.r), phy.sink.data.eq(self._rxtx.r),
).Elif(phy.tx.sink.ack, ).Elif(phy.sink.ack,
phy.tx.sink.stb.eq(0) phy.sink.stb.eq(0)
), ),
If(phy.rx.source.stb, If(phy.source.stb,
self._rxtx.w.eq(phy.rx.source.data) self._rxtx.w.eq(phy.source.data)
) )
] ]
self.comb += [ self.comb += [
self.ev.tx.trigger.eq(phy.tx.sink.stb & phy.tx.sink.ack), self.ev.tx.trigger.eq(phy.sink.stb & phy.sink.ack),
self.ev.rx.trigger.eq(phy.rx.source.stb) #phy.rx.source.ack supposed to be always 1 self.ev.rx.trigger.eq(phy.source.stb) #phy.source.ack supposed to be always 1
] ]

2
misoclib/com/uart/phy/sim.py
View File

@ -3,8 +3,6 @@ from migen.flow.actor import Sink, Source
class UARTPHYSim(Module): class UARTPHYSim(Module):
def __init__(self, pads): def __init__(self, pads):
self.dw = 8
self.tuning_word = Signal(32)
self.sink = Sink([("data", 8)]) self.sink = Sink([("data", 8)])
self.source = Source([("data", 8)]) self.source = Source([("data", 8)])

10
misoclib/soc/__init__.py
View File

@ -7,6 +7,7 @@ from migen.bank import csrgen
from migen.bus import wishbone, csr, wishbone2csr from migen.bus import wishbone, csr, wishbone2csr
from misoclib.com.uart.phy.serial import UARTPHYSerial from misoclib.com.uart.phy.serial import UARTPHYSerial
from misoclib.com.uart.phy.sim import UARTPHYSim
from misoclib.com import uart from misoclib.com import uart
from misoclib.cpu import CPU, lm32, mor1kx from misoclib.cpu import CPU, lm32, mor1kx
from misoclib.cpu.peripherals import identifier, timer from misoclib.cpu.peripherals import identifier, timer
@ -14,6 +15,12 @@ from misoclib.cpu.peripherals import identifier, timer
def mem_decoder(address, start=26, end=29): def mem_decoder(address, start=26, end=29):
return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1) return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
def is_sim(platform):
if hasattr(platform, "is_sim"):
return platform.is_sim
else:
return False
class SoC(Module): class SoC(Module):
csr_map = { csr_map = {
"crg": 0, # user "crg": 0, # user
@ -107,6 +114,9 @@ class SoC(Module):
self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone) self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
if with_uart: if with_uart:
if is_sim(platform):
self.submodules.uart_phy = UARTPHYSim(platform.request("serial"))
else:
self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate) self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy) self.submodules.uart = uart.UART(self.uart_phy)