Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

add VexRiscv submodule

Browse source
This commit is contained in:
Florent Kermarrec 2018-05-09 14:39:31 +02:00
parent d149f386c9
commit f60da4a5dc
2 changed files with 4 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
.gitmodules vendored
View file

@ -13,3 +13,6 @@
[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
path = litex/build/sim/core/modules/ethernet/tapcfg
url = https://github.com/nizox/tapcfg
[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
path = litex/soc/cores/cpu/vexriscv/verilog
url = https://github.com/m-labs/VexRiscv-verilog.git

1
litex/soc/cores/cpu/vexriscv/verilog Submodule

@ -0,0 +1 @@
Subproject commit 4811a12127eef5dfaaa8df47a59e58a1e561b0eb