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add VexRiscv submodule

This commit is contained in:
Florent Kermarrec 2018-05-09 14:39:31 +02:00
parent d149f386c9
commit f60da4a5dc
2 changed files with 4 additions and 0 deletions
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3
.gitmodules vendored
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@ -13,3 +13,6 @@
[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
path = litex/build/sim/core/modules/ethernet/tapcfg
url = https://github.com/nizox/tapcfg
[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
path = litex/soc/cores/cpu/vexriscv/verilog
url = https://github.com/m-labs/VexRiscv-verilog.git

1
litex/soc/cores/cpu/vexriscv/verilog Submodule

@ -0,0 +1 @@
Subproject commit 4811a12127eef5dfaaa8df47a59e58a1e561b0eb