targets/sim: add rom-init
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1dbf591e78
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@ -144,6 +144,8 @@ def main():
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parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
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parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
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builder_args(parser)
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builder_args(parser)
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soc_sdram_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--rom-init", default=None,
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help="rom_init file")
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parser.add_argument("--ram-init", default=None,
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parser.add_argument("--ram-init", default=None,
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help="ram_init file")
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help="ram_init file")
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parser.add_argument("--with-sdram", action="store_true",
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parser.add_argument("--with-sdram", action="store_true",
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@ -156,15 +158,17 @@ def main():
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help="enable Analyzer support")
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help="enable Analyzer support")
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args = parser.parse_args()
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args = parser.parse_args()
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kwargs = soc_sdram_argdict(args)
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sim_config = SimConfig(default_clk="sys_clk")
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sim_config = SimConfig(default_clk="sys_clk")
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sim_config.add_module("serial2console", "serial")
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sim_config.add_module("serial2console", "serial")
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integrated_main_ram_init = []
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if args.rom_init:
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kwargs["integrated_rom_init"] = get_mem_data(args.rom_init)
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kwargs["integrated_main_ram_size"] = 0x10000
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if not args.with_sdram:
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if not args.with_sdram:
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if args.ram_init is not None:
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if args.ram_init is not None:
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integrated_main_ram_init = get_mem_data(args.ram_init)
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kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init)
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integrated_main_ram_size = max(len(integrated_main_ram_init), 0x10000)
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kwargs["integrated_main_ram_size"] = max(len(kwargs["integrated_main_ram_init"]), 0x10000)
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else:
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integrated_main_ram_size = 0
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if args.with_ethernet:
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if args.with_ethernet:
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sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
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sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
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if args.with_etherbone:
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if args.with_etherbone:
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@ -174,9 +178,7 @@ def main():
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with_ethernet=args.with_ethernet,
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with_ethernet=args.with_ethernet,
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with_etherbone=args.with_etherbone,
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with_etherbone=args.with_etherbone,
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with_analyzer=args.with_analyzer,
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with_analyzer=args.with_analyzer,
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integrated_main_ram_size=integrated_main_ram_size,
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**kwargs)
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integrated_main_ram_init=integrated_main_ram_init,
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**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(sim_config=sim_config)
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builder.build(sim_config=sim_config)
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