test/test_axi: Minor cleanups.
This commit is contained in:
Florent Kermarrec
parent
d0dc5c8d95
commit
f62eca77e3
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@ -1,7 +1,7 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2019-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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@ -54,12 +54,9 @@ class Access(Burst):
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self.id = id
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class Write(Access):
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pass
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class Write(Access): pass
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class Read(Access):
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pass
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class Read(Access): pass
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# TestAXI ------------------------------------------------------------------------------------------
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@ -98,12 +95,12 @@ class TestAXI(unittest.TestCase):
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self.errors += 1
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yield
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# dut
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# DUT
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ax_burst = stream.Endpoint(ax_description(32, 32))
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ax_beat = stream.Endpoint(ax_description(32, 32))
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dut = AXIBurst2Beat(ax_burst, ax_beat)
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# generate dut input (bursts)
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# Generate DUT input (bursts).
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prng = random.Random(42)
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bursts = []
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for i in range(32):
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@ -112,12 +109,12 @@ class TestAXI(unittest.TestCase):
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bursts.append(Burst(4, BURST_WRAP, 4-1, log2_int(2)))
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bursts.append(Burst(0x80000160, BURST_WRAP, 0x3, 0b100))
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# generate expected dut output (beats for reference)
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# Generate expected DUT output (beats for reference).
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beats = []
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for burst in bursts:
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beats += burst.to_beats()
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# simulation
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# Simulation
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generators = [
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bursts_generator(ax_burst, bursts),
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beats_checker(ax_beat, beats)
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@ -128,17 +125,17 @@ class TestAXI(unittest.TestCase):
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def _test_axi2wishbone(self,
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naccesses=16, simultaneous_writes_reads=False,
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# random: 0: min (no random), 100: max.
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# burst randomness
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# Random: 0: min (no random), 100: max.
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# Burst randomness.
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id_rand_enable = False,
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len_rand_enable = False,
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data_rand_enable = False,
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# flow valid randomness
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# Flow valid randomness.
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aw_valid_random = 0,
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w_valid_random = 0,
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ar_valid_random = 0,
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r_valid_random = 0,
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# flow ready randomness
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# Flow ready randomness.
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w_ready_random = 0,
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b_ready_random = 0,
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r_ready_random = 0
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@ -149,7 +146,7 @@ class TestAXI(unittest.TestCase):
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for write in writes:
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while prng.randrange(100) < aw_valid_random:
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yield
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# send command
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# Send command.
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yield axi_port.aw.valid.eq(1)
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yield axi_port.aw.addr.eq(write.addr<<2)
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yield axi_port.aw.burst.eq(write.type)
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@ -168,7 +165,7 @@ class TestAXI(unittest.TestCase):
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for i, data in enumerate(write.data):
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while prng.randrange(100) < w_valid_random:
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yield
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# send data
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# Send data.
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yield axi_port.w.valid.eq(1)
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if (i == (len(write.data) - 1)):
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yield axi_port.w.last.eq(1)
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@ -204,7 +201,7 @@ class TestAXI(unittest.TestCase):
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for read in reads:
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while prng.randrange(100) < ar_valid_random:
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yield
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# send command
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# Send command.
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yield axi_port.ar.valid.eq(1)
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yield axi_port.ar.addr.eq(read.addr<<2)
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yield axi_port.ar.burst.eq(read.type)
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@ -225,7 +222,7 @@ class TestAXI(unittest.TestCase):
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yield
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for read in reads:
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for i, data in enumerate(read.data):
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# wait data / response
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# Wait data / response.
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yield axi_port.r.ready.eq(0)
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yield
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while (yield axi_port.r.valid) == 0:
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@ -245,7 +242,7 @@ class TestAXI(unittest.TestCase):
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if (yield axi_port.r.last) != 0:
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self.reads_last_errors += 1
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# dut
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# DUT
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class DUT(Module):
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def __init__(self):
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self.axi = AXIInterface(data_width=32, address_width=32, id_width=8)
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@ -259,7 +256,7 @@ class TestAXI(unittest.TestCase):
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dut = DUT()
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# generate writes/reads
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# Generate writes/reads.
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prng = random.Random(42)
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writes = []
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offset = 1
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@ -269,15 +266,15 @@ class TestAXI(unittest.TestCase):
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_data = [prng.randrange(2**32) if data_rand_enable else j for j in range(_len + 1)]
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writes.append(Write(offset, _data, _id, type=BURST_INCR, len=_len, size=log2_int(32//8)))
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offset += _len + 1
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# dummy reads to ensure datas have been written before the effective reads start.
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# Dummy reads to ensure datas have been written before the effective reads start.
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dummy_reads = [Read(1023, [0], 0, type=BURST_FIXED, len=0, size=log2_int(32//8)) for _ in range(32)]
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reads = writes
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# simulation
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# Simulation
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if simultaneous_writes_reads:
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dut.axi.reads_enable = True
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else:
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dut.axi.reads_enable = False # will be set by writes_data_generator
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dut.axi.reads_enable = False # Will be set by writes_data_generator.
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generators = [
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writes_cmd_generator(dut.axi, writes),
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writes_data_generator(dut.axi, writes),
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@ -291,11 +288,11 @@ class TestAXI(unittest.TestCase):
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self.assertEqual(self.reads_id_errors, 0)
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self.assertEqual(self.reads_last_errors, 0)
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# test with no randomness
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# Test with no randomness.
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def test_axi2wishbone_writes_then_reads_no_random(self):
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self._test_axi2wishbone(simultaneous_writes_reads=False)
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# test randomness one parameter at a time
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# Test randomness one parameter at a time.
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def test_axi2wishbone_writes_then_reads_random_bursts(self):
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self._test_axi2wishbone(
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simultaneous_writes_reads = False,
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@ -324,7 +321,7 @@ class TestAXI(unittest.TestCase):
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def test_axi2wishbone_random_r_valid(self):
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self._test_axi2wishbone(r_valid_random=90)
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# now let's stress things a bit... :)
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# Now let's stress things a bit... :)
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def test_axi2wishbone_random_all(self):
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self._test_axi2wishbone(
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simultaneous_writes_reads = False,
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