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migen/actorlib/spi: apply missing CSR renaming

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This commit is contained in:
Florent Kermarrec 2015-05-13 10:17:31 +02:00
parent 76302d7aa6
commit f6624b34f0
1 changed files with 7 additions and 7 deletions
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14
migen/actorlib/spi.py
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@ -66,7 +66,7 @@ class SingleGenerator(Module, AutoCSR):
regname = prefix + name regname = prefix + name
reg = CSRStorage(nbits + alignment, reset=reset, atomic_write=atomic, reg = CSRStorage(nbits + alignment, reset=reset, atomic_write=atomic,
alignment_bits=alignment, name=regname) alignment_bits=alignment, name=regname)
setattr(self, "r_"+regname, reg) setattr(self, "_"+regname, reg)
self.sync += If(self.source.ack | ~self.source.stb, self.sync += If(self.source.ack | ~self.source.stb,
getattr(target, name).eq(reg.storage)) getattr(target, name).eq(reg.storage))
@ -120,15 +120,15 @@ class _DMAController(Module):
("base", bus_aw + self.alignment_bits, base_reset, self.alignment_bits) ("base", bus_aw + self.alignment_bits, base_reset, self.alignment_bits)
] ]
self.generator = SingleGenerator(layout, mode) self.generator = SingleGenerator(layout, mode)
self.r_busy = CSRStatus() self._busy = CSRStatus()
self.length = self.generator.r_length.storage self.length = self.generator._length.storage
self.base = self.generator.r_base.storage self.base = self.generator._base.storage
if hasattr(self.generator, "trigger"): if hasattr(self.generator, "trigger"):
self.trigger = self.generator.trigger self.trigger = self.generator.trigger
def get_csrs(self): def get_csrs(self):
return self.generator.get_csrs() + [self.r_busy] return self.generator.get_csrs() + [self._busy]
class DMAReadController(_DMAController): class DMAReadController(_DMAController):
@ -148,7 +148,7 @@ class DMAReadController(_DMAController):
self.data = comp_actor.q self.data = comp_actor.q
self.busy = comp_actor.busy self.busy = comp_actor.busy
self.comb += self.r_busy.status.eq(self.busy) self.comb += self._busy.status.eq(self.busy)
class DMAWriteController(_DMAController): class DMAWriteController(_DMAController):
@ -181,4 +181,4 @@ class DMAWriteController(_DMAController):
self.data = comp_actor.d self.data = comp_actor.d
self.busy = comp_actor.busy self.busy = comp_actor.busy
self.comb += self.r_busy.status.eq(self.busy) self.comb += self._busy.status.eq(self.busy)