interconnect: add bus/bank components from Migen
This commit is contained in:
Sebastien Bourdeauducq
parent
ecdc4101b4
commit
f69674e89c
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@ -0,0 +1,147 @@
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from migen.util.misc import xdir
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from migen.fhdl.std import *
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from migen.fhdl.tracer import get_obj_var_name
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class _CSRBase(HUID):
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def __init__(self, size, name):
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HUID.__init__(self)
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self.name = get_obj_var_name(name)
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if self.name is None:
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raise ValueError("Cannot extract CSR name from code, need to specify.")
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self.size = size
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class CSR(_CSRBase):
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def __init__(self, size=1, name=None):
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_CSRBase.__init__(self, size, name)
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self.re = Signal(name=self.name + "_re")
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self.r = Signal(self.size, name=self.name + "_r")
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self.w = Signal(self.size, name=self.name + "_w")
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class _CompoundCSR(_CSRBase, Module):
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def __init__(self, size, name):
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_CSRBase.__init__(self, size, name)
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self.simple_csrs = []
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def get_simple_csrs(self):
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if not self.finalized:
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raise FinalizeError
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return self.simple_csrs
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def do_finalize(self, busword):
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raise NotImplementedError
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class CSRStatus(_CompoundCSR):
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def __init__(self, size=1, reset=0, name=None):
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_CompoundCSR.__init__(self, size, name)
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self.status = Signal(self.size, reset=reset)
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def do_finalize(self, busword):
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nwords = (self.size + busword - 1)//busword
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for i in reversed(range(nwords)):
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nbits = min(self.size - i*busword, busword)
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sc = CSR(nbits, self.name + str(i) if nwords > 1 else self.name)
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self.comb += sc.w.eq(self.status[i*busword:i*busword+nbits])
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self.simple_csrs.append(sc)
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class CSRStorage(_CompoundCSR):
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def __init__(self, size=1, reset=0, atomic_write=False, write_from_dev=False, alignment_bits=0, name=None):
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_CompoundCSR.__init__(self, size, name)
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self.alignment_bits = alignment_bits
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self.storage_full = Signal(self.size, reset=reset)
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self.storage = Signal(self.size - self.alignment_bits, reset=reset >> alignment_bits)
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self.comb += self.storage.eq(self.storage_full[self.alignment_bits:])
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self.atomic_write = atomic_write
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self.re = Signal()
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if write_from_dev:
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self.we = Signal()
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self.dat_w = Signal(self.size - self.alignment_bits)
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self.sync += If(self.we, self.storage_full.eq(self.dat_w << self.alignment_bits))
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def do_finalize(self, busword):
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nwords = (self.size + busword - 1)//busword
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if nwords > 1 and self.atomic_write:
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backstore = Signal(self.size - busword, name=self.name + "_backstore")
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for i in reversed(range(nwords)):
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nbits = min(self.size - i*busword, busword)
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sc = CSR(nbits, self.name + str(i) if nwords else self.name)
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self.simple_csrs.append(sc)
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lo = i*busword
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hi = lo+nbits
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# read
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if lo >= self.alignment_bits:
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self.comb += sc.w.eq(self.storage_full[lo:hi])
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elif hi > self.alignment_bits:
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self.comb += sc.w.eq(Cat(Replicate(0, hi - self.alignment_bits),
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self.storage_full[self.alignment_bits:hi]))
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else:
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self.comb += sc.w.eq(0)
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# write
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if nwords > 1 and self.atomic_write:
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if i:
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self.sync += If(sc.re, backstore[lo-busword:hi-busword].eq(sc.r))
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else:
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self.sync += If(sc.re, self.storage_full.eq(Cat(sc.r, backstore)))
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else:
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self.sync += If(sc.re, self.storage_full[lo:hi].eq(sc.r))
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self.sync += self.re.eq(sc.re)
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def csrprefix(prefix, csrs, done):
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for csr in csrs:
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if csr.huid not in done:
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csr.name = prefix + csr.name
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done.add(csr.huid)
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def memprefix(prefix, memories, done):
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for memory in memories:
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if memory.huid not in done:
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memory.name_override = prefix + memory.name_override
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done.add(memory.huid)
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def _make_gatherer(method, cls, prefix_cb):
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def gatherer(self):
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try:
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exclude = self.autocsr_exclude
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except AttributeError:
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exclude = {}
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try:
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prefixed = self.__prefixed
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except AttributeError:
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prefixed = self.__prefixed = set()
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r = []
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for k, v in xdir(self, True):
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if k not in exclude:
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if isinstance(v, cls):
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r.append(v)
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elif hasattr(v, method) and callable(getattr(v, method)):
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items = getattr(v, method)()
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prefix_cb(k + "_", items, prefixed)
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r += items
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return sorted(r, key=lambda x: x.huid)
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return gatherer
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class AutoCSR:
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get_memories = _make_gatherer("get_memories", Memory, memprefix)
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get_csrs = _make_gatherer("get_csrs", _CSRBase, csrprefix)
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class GenericBank(Module):
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def __init__(self, description, busword):
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# Turn description into simple CSRs and claim ownership of compound CSR modules
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self.simple_csrs = []
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for c in description:
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if isinstance(c, CSR):
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self.simple_csrs.append(c)
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else:
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c.finalize(busword)
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self.simple_csrs += c.get_simple_csrs()
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self.submodules += c
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self.decode_bits = bits_for(len(self.simple_csrs)-1)
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@ -0,0 +1,215 @@
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from migen.fhdl.std import *
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from migen.bus.transactions import *
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from migen.bank.description import CSRStorage
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from migen.genlib.record import *
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from migen.genlib.misc import chooser
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from misoc.interconnect import csr
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_layout = [
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("adr", "address_width", DIR_M_TO_S),
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("we", 1, DIR_M_TO_S),
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("dat_w", "data_width", DIR_M_TO_S),
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("dat_r", "data_width", DIR_S_TO_M)
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]
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class Interface(Record):
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def __init__(self, data_width=8, address_width=14):
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Record.__init__(self, set_layout_parameters(_layout,
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data_width=data_width, address_width=address_width))
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class Interconnect(Module):
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def __init__(self, master, slaves):
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self.comb += master.connect(*slaves)
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class Initiator(Module):
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def __init__(self, generator, bus=None):
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self.generator = generator
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if bus is None:
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bus = Interface()
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self.bus = bus
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self.transaction = None
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self.read_data_ready = False
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self.done = False
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def do_simulation(self, selfp):
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if not self.done:
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if self.transaction is not None:
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if isinstance(self.transaction, TRead):
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if self.read_data_ready:
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self.transaction.data = selfp.bus.dat_r
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self.transaction = None
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self.read_data_ready = False
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else:
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self.read_data_ready = True
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else:
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selfp.bus.we = 0
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self.transaction = None
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if self.transaction is None:
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try:
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self.transaction = next(self.generator)
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except StopIteration:
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self.transaction = None
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raise StopSimulation
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if self.transaction is not None:
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selfp.bus.adr = self.transaction.address
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if isinstance(self.transaction, TWrite):
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selfp.bus.we = 1
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selfp.bus.dat_w = self.transaction.data
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class SRAM(Module):
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def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
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if bus is None:
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bus = Interface()
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self.bus = bus
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data_width = flen(self.bus.dat_w)
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if isinstance(mem_or_size, Memory):
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mem = mem_or_size
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else:
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mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
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csrw_per_memw = (mem.width + data_width - 1)//data_width
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word_bits = log2_int(csrw_per_memw)
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page_bits = log2_int((mem.depth*csrw_per_memw + 511)//512, False)
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if page_bits:
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self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
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else:
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self._page = None
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if read_only is None:
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if hasattr(mem, "bus_read_only"):
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read_only = mem.bus_read_only
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else:
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read_only = False
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###
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port = mem.get_port(write_capable=not read_only)
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self.specials += mem, port
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sel = Signal()
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sel_r = Signal()
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self.sync += sel_r.eq(sel)
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self.comb += sel.eq(self.bus.adr[9:] == address)
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if word_bits:
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word_index = Signal(word_bits)
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word_expanded = Signal(csrw_per_memw*data_width)
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self.sync += word_index.eq(self.bus.adr[:word_bits])
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self.comb += [
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word_expanded.eq(port.dat_r),
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If(sel_r,
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chooser(word_expanded, word_index, self.bus.dat_r, n=csrw_per_memw, reverse=True)
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)
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]
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if not read_only:
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wregs = []
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for i in range(csrw_per_memw-1):
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wreg = Signal(data_width)
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self.sync += If(sel & self.bus.we & (self.bus.adr[:word_bits] == i), wreg.eq(self.bus.dat_w))
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wregs.append(wreg)
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memword_chunks = [self.bus.dat_w] + list(reversed(wregs))
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self.comb += [
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port.we.eq(sel & self.bus.we & (self.bus.adr[:word_bits] == csrw_per_memw - 1)),
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port.dat_w.eq(Cat(*memword_chunks))
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]
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else:
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self.comb += If(sel_r, self.bus.dat_r.eq(port.dat_r))
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if not read_only:
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self.comb += [
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port.we.eq(sel & self.bus.we),
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port.dat_w.eq(self.bus.dat_w)
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]
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if self._page is None:
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self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+flen(port.adr)])
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else:
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pv = self._page.storage
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self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+flen(port.adr)-flen(pv)], pv))
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def get_csrs(self):
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if self._page is None:
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return []
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else:
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return [self._page]
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class CSRBank(csr.GenericBank):
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def __init__(self, description, address=0, bus=None):
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if bus is None:
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bus = Interface()
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self.bus = bus
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###
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GenericBank.__init__(self, description, flen(self.bus.dat_w))
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sel = Signal()
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self.comb += sel.eq(self.bus.adr[9:] == address)
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for i, c in enumerate(self.simple_csrs):
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self.comb += [
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c.r.eq(self.bus.dat_w[:c.size]),
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c.re.eq(sel & \
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self.bus.we & \
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(self.bus.adr[:self.decode_bits] == i))
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]
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brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(self.simple_csrs))
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self.sync += [
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self.bus.dat_r.eq(0),
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If(sel, Case(self.bus.adr[:self.decode_bits], brcases))
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]
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# address_map(name, memory) returns the CSR offset at which to map
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# the CSR object (register bank or memory).
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# If memory=None, the object is the register bank of object source.name.
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# Otherwise, it is a memory object belonging to source.name.
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# address_map is called exactly once for each object at each call to
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# scan(), so it can have side effects.
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class CSRBankArray(Module):
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def __init__(self, source, address_map, *ifargs, **ifkwargs):
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self.source = source
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self.address_map = address_map
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self.scan(ifargs, ifkwargs)
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def scan(self, ifargs, ifkwargs):
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self.banks = []
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self.srams = []
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for name, obj in xdir(self.source, True):
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if hasattr(obj, "get_csrs"):
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csrs = obj.get_csrs()
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else:
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csrs = []
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if hasattr(obj, "get_memories"):
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memories = obj.get_memories()
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for memory in memories:
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mapaddr = self.address_map(name, memory)
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if mapaddr is None:
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continue
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sram_bus = csr.Interface(*ifargs, **ifkwargs)
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mmap = csr.SRAM(memory, mapaddr, bus=sram_bus)
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self.submodules += mmap
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csrs += mmap.get_csrs()
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self.srams.append((name, memory, mapaddr, mmap))
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if csrs:
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mapaddr = self.address_map(name, None)
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if mapaddr is None:
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continue
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bank_bus = csr.Interface(*ifargs, **ifkwargs)
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rmap = Bank(csrs, mapaddr, bus=bank_bus)
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self.submodules += rmap
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self.banks.append((name, csrs, mapaddr, rmap))
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def get_rmaps(self):
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return [rmap for name, csrs, mapaddr, rmap in self.banks]
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def get_mmaps(self):
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return [mmap for name, memory, mapaddr, mmap in self.srams]
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def get_buses(self):
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return [i.bus for i in self.get_rmaps() + self.get_mmaps()]
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@ -0,0 +1,83 @@
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from migen.util.misc import xdir
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.misc import optree
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class _EventSource(HUID):
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def __init__(self):
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HUID.__init__(self)
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self.status = Signal() # value in the status register
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self.pending = Signal() # value in the pending register + assert irq if unmasked
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self.trigger = Signal() # trigger signal interface to the user design
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self.clear = Signal() # clearing attempt by W1C to pending register, ignored by some event sources
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# set on a positive trigger pulse
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class EventSourcePulse(Module, _EventSource):
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def __init__(self):
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_EventSource.__init__(self)
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self.comb += self.status.eq(0)
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self.sync += [
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If(self.clear, self.pending.eq(0)),
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If(self.trigger, self.pending.eq(1))
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]
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# set on the falling edge of the trigger, status = trigger
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class EventSourceProcess(Module, _EventSource):
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def __init__(self):
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_EventSource.__init__(self)
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self.comb += self.status.eq(self.trigger)
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old_trigger = Signal()
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self.sync += [
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If(self.clear, self.pending.eq(0)),
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old_trigger.eq(self.trigger),
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If(~self.trigger & old_trigger, self.pending.eq(1))
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]
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# all status set by external trigger
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class EventSourceLevel(Module, _EventSource):
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def __init__(self):
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_EventSource.__init__(self)
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self.comb += [
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self.status.eq(self.trigger),
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self.pending.eq(self.trigger)
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]
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class EventManager(Module, AutoCSR):
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def __init__(self):
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self.irq = Signal()
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def do_finalize(self):
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sources_u = [v for k, v in xdir(self, True) if isinstance(v, _EventSource)]
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sources = sorted(sources_u, key=lambda x: x.huid)
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n = len(sources)
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self.status = CSR(n)
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self.pending = CSR(n)
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self.enable = CSRStorage(n)
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for i, source in enumerate(sources):
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self.comb += [
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self.status.w[i].eq(source.status),
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If(self.pending.re & self.pending.r[i], source.clear.eq(1)),
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self.pending.w[i].eq(source.pending)
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]
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irqs = [self.pending.w[i] & self.enable.storage[i] for i in range(n)]
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self.comb += self.irq.eq(optree("|", irqs))
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def __setattr__(self, name, value):
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object.__setattr__(self, name, value)
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if isinstance(value, _EventSource):
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if self.finalized:
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raise FinalizeError
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self.submodules += value
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class SharedIRQ(Module):
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def __init__(self, *event_managers):
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self.irq = Signal()
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self.comb += self.irq.eq(optree("|", [ev.irq for ev in event_managers]))
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@ -0,0 +1,718 @@
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from migen.fhdl.std import *
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from migen.genlib import roundrobin
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from migen.genlib.record import *
|
||||
from migen.genlib.misc import split, displacer, optree, chooser
|
||||
from migen.genlib.misc import FlipFlop, Counter
|
||||
from migen.genlib.fsm import FSM, NextState
|
||||
from migen.bus.transactions import *
|
||||
|
||||
from misoc.interconnect import csr
|
||||
|
||||
|
||||
_layout = [
|
||||
("adr", 30, DIR_M_TO_S),
|
||||
("dat_w", "data_width", DIR_M_TO_S),
|
||||
("dat_r", "data_width", DIR_S_TO_M),
|
||||
("sel", "sel_width", DIR_M_TO_S),
|
||||
("cyc", 1, DIR_M_TO_S),
|
||||
("stb", 1, DIR_M_TO_S),
|
||||
("ack", 1, DIR_S_TO_M),
|
||||
("we", 1, DIR_M_TO_S),
|
||||
("cti", 3, DIR_M_TO_S),
|
||||
("bte", 2, DIR_M_TO_S),
|
||||
("err", 1, DIR_S_TO_M)
|
||||
]
|
||||
|
||||
|
||||
class Interface(Record):
|
||||
def __init__(self, data_width=32):
|
||||
Record.__init__(self, set_layout_parameters(_layout,
|
||||
data_width=data_width,
|
||||
sel_width=data_width//8))
|
||||
|
||||
|
||||
class InterconnectPointToPoint(Module):
|
||||
def __init__(self, master, slave):
|
||||
self.comb += master.connect(slave)
|
||||
|
||||
|
||||
class Arbiter(Module):
|
||||
def __init__(self, masters, target):
|
||||
self.submodules.rr = roundrobin.RoundRobin(len(masters))
|
||||
|
||||
# mux master->slave signals
|
||||
for name, size, direction in _layout:
|
||||
if direction == DIR_M_TO_S:
|
||||
choices = Array(getattr(m, name) for m in masters)
|
||||
self.comb += getattr(target, name).eq(choices[self.rr.grant])
|
||||
|
||||
# connect slave->master signals
|
||||
for name, size, direction in _layout:
|
||||
if direction == DIR_S_TO_M:
|
||||
source = getattr(target, name)
|
||||
for i, m in enumerate(masters):
|
||||
dest = getattr(m, name)
|
||||
if name == "ack" or name == "err":
|
||||
self.comb += dest.eq(source & (self.rr.grant == i))
|
||||
else:
|
||||
self.comb += dest.eq(source)
|
||||
|
||||
# connect bus requests to round-robin selector
|
||||
reqs = [m.cyc for m in masters]
|
||||
self.comb += self.rr.request.eq(Cat(*reqs))
|
||||
|
||||
|
||||
class Decoder(Module):
|
||||
# slaves is a list of pairs:
|
||||
# 0) function that takes the address signal and returns a FHDL expression
|
||||
# that evaluates to 1 when the slave is selected and 0 otherwise.
|
||||
# 1) wishbone.Slave reference.
|
||||
# register adds flip-flops after the address comparators. Improves timing,
|
||||
# but breaks Wishbone combinatorial feedback.
|
||||
def __init__(self, master, slaves, register=False):
|
||||
ns = len(slaves)
|
||||
slave_sel = Signal(ns)
|
||||
slave_sel_r = Signal(ns)
|
||||
|
||||
# decode slave addresses
|
||||
self.comb += [slave_sel[i].eq(fun(master.adr))
|
||||
for i, (fun, bus) in enumerate(slaves)]
|
||||
if register:
|
||||
self.sync += slave_sel_r.eq(slave_sel)
|
||||
else:
|
||||
self.comb += slave_sel_r.eq(slave_sel)
|
||||
|
||||
# connect master->slaves signals except cyc
|
||||
for slave in slaves:
|
||||
for name, size, direction in _layout:
|
||||
if direction == DIR_M_TO_S and name != "cyc":
|
||||
self.comb += getattr(slave[1], name).eq(getattr(master, name))
|
||||
|
||||
# combine cyc with slave selection signals
|
||||
self.comb += [slave[1].cyc.eq(master.cyc & slave_sel[i])
|
||||
for i, slave in enumerate(slaves)]
|
||||
|
||||
# generate master ack (resp. err) by ORing all slave acks (resp. errs)
|
||||
self.comb += [
|
||||
master.ack.eq(optree("|", [slave[1].ack for slave in slaves])),
|
||||
master.err.eq(optree("|", [slave[1].err for slave in slaves]))
|
||||
]
|
||||
|
||||
# mux (1-hot) slave data return
|
||||
masked = [Replicate(slave_sel_r[i], flen(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
|
||||
self.comb += master.dat_r.eq(optree("|", masked))
|
||||
|
||||
|
||||
class InterconnectShared(Module):
|
||||
def __init__(self, masters, slaves, register=False):
|
||||
shared = Interface()
|
||||
self.submodules += Arbiter(masters, shared)
|
||||
self.submodules += Decoder(shared, slaves, register)
|
||||
|
||||
|
||||
class Crossbar(Module):
|
||||
def __init__(self, masters, slaves, register=False):
|
||||
matches, busses = zip(*slaves)
|
||||
access = [[Interface() for j in slaves] for i in masters]
|
||||
# decode each master into its access row
|
||||
for row, master in zip(access, masters):
|
||||
row = list(zip(matches, row))
|
||||
self.submodules += Decoder(master, row, register)
|
||||
# arbitrate each access column onto its slave
|
||||
for column, bus in zip(zip(*access), busses):
|
||||
self.submodules += Arbiter(column, bus)
|
||||
|
||||
|
||||
class DownConverter(Module):
|
||||
"""DownConverter
|
||||
|
||||
This module splits Wishbone accesses from a master interface to a smaller
|
||||
slave interface.
|
||||
|
||||
Writes:
|
||||
Writes from master are splitted N writes to the slave. Access is acked when the last
|
||||
access is acked by the slave.
|
||||
|
||||
Reads:
|
||||
Read from master are splitted in N reads to the the slave. Read datas from
|
||||
the slave are cached before being presented concatenated on the last access.
|
||||
|
||||
TODO:
|
||||
Manage err signal? (Not implemented since we generally don't use it on Migen/MiSoC modules)
|
||||
"""
|
||||
def __init__(self, master, slave):
|
||||
dw_from = flen(master.dat_r)
|
||||
dw_to = flen(slave.dat_w)
|
||||
ratio = dw_from//dw_to
|
||||
|
||||
# # #
|
||||
|
||||
read = Signal()
|
||||
write = Signal()
|
||||
|
||||
counter = Counter(max=ratio)
|
||||
self.submodules += counter
|
||||
counter_done = Signal()
|
||||
self.comb += counter_done.eq(counter.value == ratio-1)
|
||||
|
||||
# Main FSM
|
||||
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
||||
fsm.act("IDLE",
|
||||
counter.reset.eq(1),
|
||||
If(master.stb & master.cyc,
|
||||
If(master.we,
|
||||
NextState("WRITE")
|
||||
).Else(
|
||||
NextState("READ")
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("WRITE",
|
||||
write.eq(1),
|
||||
slave.we.eq(1),
|
||||
slave.cyc.eq(1),
|
||||
If(master.stb & master.cyc,
|
||||
slave.stb.eq(1),
|
||||
If(slave.ack,
|
||||
counter.ce.eq(1),
|
||||
If(counter_done,
|
||||
master.ack.eq(1),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
).Elif(~master.cyc,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("READ",
|
||||
read.eq(1),
|
||||
slave.cyc.eq(1),
|
||||
If(master.stb & master.cyc,
|
||||
slave.stb.eq(1),
|
||||
If(slave.ack,
|
||||
counter.ce.eq(1),
|
||||
If(counter_done,
|
||||
master.ack.eq(1),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
).Elif(~master.cyc,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
# Address
|
||||
self.comb += [
|
||||
If(counter_done,
|
||||
slave.cti.eq(7) # indicate end of burst
|
||||
).Else(
|
||||
slave.cti.eq(2)
|
||||
),
|
||||
slave.adr.eq(Cat(counter.value, master.adr))
|
||||
]
|
||||
|
||||
# Datapath
|
||||
cases = {}
|
||||
for i in range(ratio):
|
||||
cases[i] = [
|
||||
slave.sel.eq(master.sel[i*dw_to//8:(i+1)*dw_to]),
|
||||
slave.dat_w.eq(master.dat_w[i*dw_to:(i+1)*dw_to])
|
||||
]
|
||||
self.comb += Case(counter.value, cases)
|
||||
|
||||
|
||||
cached_data = Signal(dw_from)
|
||||
self.comb += master.dat_r.eq(Cat(cached_data[dw_to:], slave.dat_r))
|
||||
self.sync += \
|
||||
If(read & counter.ce,
|
||||
cached_data.eq(master.dat_r)
|
||||
)
|
||||
|
||||
|
||||
class UpConverter(Module):
|
||||
"""UpConverter
|
||||
|
||||
This module up-converts wishbone accesses and bursts from a master interface
|
||||
to a wider slave interface. This allows efficient use wishbone bursts.
|
||||
|
||||
Writes:
|
||||
Wishbone writes are cached before being written to the slave. Access to
|
||||
the slave is done at the end of a burst or when address reach end of burst
|
||||
addressing.
|
||||
|
||||
Reads:
|
||||
Cache is refilled only at the beginning of each burst, the subsequent
|
||||
reads of a burst use the cached data.
|
||||
|
||||
TODO:
|
||||
Manage err signal? (Not implemented since we generally don't use it on Migen/MiSoC modules)
|
||||
"""
|
||||
def __init__(self, master, slave):
|
||||
dw_from = flen(master.dat_r)
|
||||
dw_to = flen(slave.dat_w)
|
||||
ratio = dw_to//dw_from
|
||||
ratiobits = log2_int(ratio)
|
||||
|
||||
# # #
|
||||
|
||||
write = Signal()
|
||||
evict = Signal()
|
||||
refill = Signal()
|
||||
read = Signal()
|
||||
|
||||
address = FlipFlop(30)
|
||||
self.submodules += address
|
||||
self.comb += address.d.eq(master.adr)
|
||||
|
||||
counter = Counter(max=ratio)
|
||||
self.submodules += counter
|
||||
counter_offset = Signal(max=ratio)
|
||||
counter_done = Signal()
|
||||
self.comb += [
|
||||
counter_offset.eq(address.q),
|
||||
counter_done.eq((counter.value + counter_offset) == ratio-1)
|
||||
]
|
||||
|
||||
cached_data = Signal(dw_to)
|
||||
cached_sel = Signal(dw_to//8)
|
||||
|
||||
end_of_burst = Signal()
|
||||
self.comb += end_of_burst.eq(~master.cyc |
|
||||
(master.stb & master.cyc & master.ack & ((master.cti == 7) | counter_done)))
|
||||
|
||||
|
||||
need_refill = FlipFlop(reset=1)
|
||||
self.submodules += need_refill
|
||||
self.comb += [
|
||||
need_refill.reset.eq(end_of_burst),
|
||||
need_refill.d.eq(0)
|
||||
]
|
||||
|
||||
# Main FSM
|
||||
self.submodules.fsm = fsm = FSM()
|
||||
fsm.act("IDLE",
|
||||
counter.reset.eq(1),
|
||||
If(master.stb & master.cyc,
|
||||
address.ce.eq(1),
|
||||
If(master.we,
|
||||
NextState("WRITE")
|
||||
).Else(
|
||||
If(need_refill.q,
|
||||
NextState("REFILL")
|
||||
).Else(
|
||||
NextState("READ")
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("WRITE",
|
||||
If(master.stb & master.cyc,
|
||||
write.eq(1),
|
||||
counter.ce.eq(1),
|
||||
master.ack.eq(1),
|
||||
If(counter_done,
|
||||
NextState("EVICT")
|
||||
)
|
||||
).Elif(~master.cyc,
|
||||
NextState("EVICT")
|
||||
)
|
||||
)
|
||||
fsm.act("EVICT",
|
||||
evict.eq(1),
|
||||
slave.stb.eq(1),
|
||||
slave.we.eq(1),
|
||||
slave.cyc.eq(1),
|
||||
slave.dat_w.eq(cached_data),
|
||||
slave.sel.eq(cached_sel),
|
||||
If(slave.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("REFILL",
|
||||
refill.eq(1),
|
||||
slave.stb.eq(1),
|
||||
slave.cyc.eq(1),
|
||||
If(slave.ack,
|
||||
need_refill.ce.eq(1),
|
||||
NextState("READ")
|
||||
)
|
||||
)
|
||||
fsm.act("READ",
|
||||
read.eq(1),
|
||||
If(master.stb & master.cyc,
|
||||
master.ack.eq(1)
|
||||
),
|
||||
NextState("IDLE")
|
||||
)
|
||||
|
||||
# Address
|
||||
self.comb += [
|
||||
slave.cti.eq(7), # we are not able to generate bursts since up-converting
|
||||
slave.adr.eq(address.q[ratiobits:])
|
||||
]
|
||||
|
||||
# Datapath
|
||||
cached_datas = [FlipFlop(dw_from) for i in range(ratio)]
|
||||
cached_sels = [FlipFlop(dw_from//8) for i in range(ratio)]
|
||||
self.submodules += cached_datas, cached_sels
|
||||
|
||||
cases = {}
|
||||
for i in range(ratio):
|
||||
write_sel = Signal()
|
||||
cases[i] = write_sel.eq(1)
|
||||
self.comb += [
|
||||
cached_sels[i].reset.eq(counter.reset),
|
||||
If(write,
|
||||
cached_datas[i].d.eq(master.dat_w),
|
||||
).Else(
|
||||
cached_datas[i].d.eq(slave.dat_r[dw_from*i:dw_from*(i+1)])
|
||||
),
|
||||
cached_sels[i].d.eq(master.sel),
|
||||
If((write & write_sel) | refill,
|
||||
cached_datas[i].ce.eq(1),
|
||||
cached_sels[i].ce.eq(1)
|
||||
)
|
||||
]
|
||||
self.comb += Case(counter.value + counter_offset, cases)
|
||||
|
||||
cases = {}
|
||||
for i in range(ratio):
|
||||
cases[i] = master.dat_r.eq(cached_datas[i].q)
|
||||
self.comb += Case(address.q[:ratiobits], cases)
|
||||
|
||||
self.comb += [
|
||||
cached_data.eq(Cat([cached_data.q for cached_data in cached_datas])),
|
||||
cached_sel.eq(Cat([cached_sel.q for cached_sel in cached_sels]))
|
||||
]
|
||||
|
||||
|
||||
class Converter(Module):
|
||||
"""Converter
|
||||
|
||||
This module is a wrapper for DownConverter and UpConverter.
|
||||
It should preferably be used rather than direct instantiations
|
||||
of specific converters.
|
||||
"""
|
||||
def __init__(self, master, slave):
|
||||
self.master = master
|
||||
self.slave = slave
|
||||
|
||||
# # #
|
||||
|
||||
dw_from = flen(master.dat_r)
|
||||
dw_to = flen(slave.dat_r)
|
||||
if dw_from > dw_to:
|
||||
downconverter = DownConverter(master, slave)
|
||||
self.submodules += downconverter
|
||||
elif dw_from < dw_to:
|
||||
upconverter = UpConverter(master, slave)
|
||||
self.submodules += upconverter
|
||||
else:
|
||||
Record.connect(master, slave)
|
||||
|
||||
|
||||
class Cache(Module):
|
||||
"""Cache
|
||||
|
||||
This module is a write-back wishbone cache that can be used as a L2 cache.
|
||||
Cachesize (in 32-bit words) is the size of the data store and must be a power of 2
|
||||
"""
|
||||
def __init__(self, cachesize, master, slave):
|
||||
self.master = master
|
||||
self.slave = slave
|
||||
|
||||
###
|
||||
|
||||
dw_from = flen(master.dat_r)
|
||||
dw_to = flen(slave.dat_r)
|
||||
if dw_to > dw_from and (dw_to % dw_from) != 0:
|
||||
raise ValueError("Slave data width must be a multiple of {dw}".format(dw=dw_from))
|
||||
if dw_to < dw_from and (dw_from % dw_to) != 0:
|
||||
raise ValueError("Master data width must be a multiple of {dw}".format(dw=dw_to))
|
||||
|
||||
# Split address:
|
||||
# TAG | LINE NUMBER | LINE OFFSET
|
||||
offsetbits = log2_int(max(dw_to//dw_from, 1))
|
||||
addressbits = flen(slave.adr) + offsetbits
|
||||
linebits = log2_int(cachesize) - offsetbits
|
||||
tagbits = addressbits - linebits
|
||||
wordbits = log2_int(max(dw_from//dw_to, 1))
|
||||
adr_offset, adr_line, adr_tag = split(master.adr, offsetbits, linebits, tagbits)
|
||||
word = Signal(wordbits) if wordbits else None
|
||||
|
||||
# Data memory
|
||||
data_mem = Memory(dw_to*2**wordbits, 2**linebits)
|
||||
data_port = data_mem.get_port(write_capable=True, we_granularity=8)
|
||||
self.specials += data_mem, data_port
|
||||
|
||||
write_from_slave = Signal()
|
||||
if adr_offset is None:
|
||||
adr_offset_r = None
|
||||
else:
|
||||
adr_offset_r = Signal(offsetbits)
|
||||
self.sync += adr_offset_r.eq(adr_offset)
|
||||
|
||||
self.comb += [
|
||||
data_port.adr.eq(adr_line),
|
||||
If(write_from_slave,
|
||||
displacer(slave.dat_r, word, data_port.dat_w),
|
||||
displacer(Replicate(1, dw_to//8), word, data_port.we)
|
||||
).Else(
|
||||
data_port.dat_w.eq(Replicate(master.dat_w, max(dw_to//dw_from, 1))),
|
||||
If(master.cyc & master.stb & master.we & master.ack,
|
||||
displacer(master.sel, adr_offset, data_port.we, 2**offsetbits, reverse=True)
|
||||
)
|
||||
),
|
||||
chooser(data_port.dat_r, word, slave.dat_w),
|
||||
slave.sel.eq(2**(dw_to//8)-1),
|
||||
chooser(data_port.dat_r, adr_offset_r, master.dat_r, reverse=True)
|
||||
]
|
||||
|
||||
|
||||
# Tag memory
|
||||
tag_layout = [("tag", tagbits), ("dirty", 1)]
|
||||
tag_mem = Memory(layout_len(tag_layout), 2**linebits)
|
||||
tag_port = tag_mem.get_port(write_capable=True)
|
||||
self.specials += tag_mem, tag_port
|
||||
tag_do = Record(tag_layout)
|
||||
tag_di = Record(tag_layout)
|
||||
self.comb += [
|
||||
tag_do.raw_bits().eq(tag_port.dat_r),
|
||||
tag_port.dat_w.eq(tag_di.raw_bits())
|
||||
]
|
||||
|
||||
self.comb += [
|
||||
tag_port.adr.eq(adr_line),
|
||||
tag_di.tag.eq(adr_tag)
|
||||
]
|
||||
if word is not None:
|
||||
self.comb += slave.adr.eq(Cat(word, adr_line, tag_do.tag))
|
||||
else:
|
||||
self.comb += slave.adr.eq(Cat(adr_line, tag_do.tag))
|
||||
|
||||
# slave word computation, word_clr and word_inc will be simplified
|
||||
# at synthesis when wordbits=0
|
||||
word_clr = Signal()
|
||||
word_inc = Signal()
|
||||
if word is not None:
|
||||
self.sync += \
|
||||
If(word_clr,
|
||||
word.eq(0),
|
||||
).Elif(word_inc,
|
||||
word.eq(word+1)
|
||||
)
|
||||
|
||||
def word_is_last(word):
|
||||
if word is not None:
|
||||
return word == 2**wordbits-1
|
||||
else:
|
||||
return 1
|
||||
|
||||
# Control FSM
|
||||
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
||||
fsm.act("IDLE",
|
||||
If(master.cyc & master.stb,
|
||||
NextState("TEST_HIT")
|
||||
)
|
||||
)
|
||||
fsm.act("TEST_HIT",
|
||||
word_clr.eq(1),
|
||||
If(tag_do.tag == adr_tag,
|
||||
master.ack.eq(1),
|
||||
If(master.we,
|
||||
tag_di.dirty.eq(1),
|
||||
tag_port.we.eq(1)
|
||||
),
|
||||
NextState("IDLE")
|
||||
).Else(
|
||||
If(tag_do.dirty,
|
||||
NextState("EVICT")
|
||||
).Else(
|
||||
NextState("REFILL_WRTAG")
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("EVICT",
|
||||
slave.stb.eq(1),
|
||||
slave.cyc.eq(1),
|
||||
slave.we.eq(1),
|
||||
If(slave.ack,
|
||||
word_inc.eq(1),
|
||||
If(word_is_last(word),
|
||||
NextState("REFILL_WRTAG")
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("REFILL_WRTAG",
|
||||
# Write the tag first to set the slave address
|
||||
tag_port.we.eq(1),
|
||||
word_clr.eq(1),
|
||||
NextState("REFILL")
|
||||
)
|
||||
fsm.act("REFILL",
|
||||
slave.stb.eq(1),
|
||||
slave.cyc.eq(1),
|
||||
slave.we.eq(0),
|
||||
If(slave.ack,
|
||||
write_from_slave.eq(1),
|
||||
word_inc.eq(1),
|
||||
If(word_is_last(word),
|
||||
NextState("TEST_HIT"),
|
||||
).Else(
|
||||
NextState("REFILL")
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
|
||||
class Tap(Module):
|
||||
def __init__(self, bus, handler=print):
|
||||
self.bus = bus
|
||||
self.handler = handler
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
if selfp.bus.ack:
|
||||
assert(selfp.bus.cyc and selfp.bus.stb)
|
||||
if selfp.bus.we:
|
||||
transaction = TWrite(selfp.bus.adr,
|
||||
selfp.bus.dat_w,
|
||||
selfp.bus.sel)
|
||||
else:
|
||||
transaction = TRead(selfp.bus.adr,
|
||||
selfp.bus.dat_r)
|
||||
self.handler(transaction)
|
||||
do_simulation.passive = True
|
||||
|
||||
|
||||
class Initiator(Module):
|
||||
def __init__(self, generator, bus=None):
|
||||
self.generator = generator
|
||||
if bus is None:
|
||||
bus = Interface()
|
||||
self.bus = bus
|
||||
self.transaction_start = 0
|
||||
self.transaction = None
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
if self.transaction is None or selfp.bus.ack:
|
||||
if self.transaction is not None:
|
||||
self.transaction.latency = selfp.simulator.cycle_counter - self.transaction_start - 1
|
||||
if isinstance(self.transaction, TRead):
|
||||
self.transaction.data = selfp.bus.dat_r
|
||||
try:
|
||||
self.transaction = next(self.generator)
|
||||
except StopIteration:
|
||||
selfp.bus.cyc = 0
|
||||
selfp.bus.stb = 0
|
||||
raise StopSimulation
|
||||
if self.transaction is not None:
|
||||
self.transaction_start = selfp.simulator.cycle_counter
|
||||
selfp.bus.cyc = 1
|
||||
selfp.bus.stb = 1
|
||||
selfp.bus.adr = self.transaction.address
|
||||
if isinstance(self.transaction, TWrite):
|
||||
selfp.bus.we = 1
|
||||
selfp.bus.sel = self.transaction.sel
|
||||
selfp.bus.dat_w = self.transaction.data
|
||||
else:
|
||||
selfp.bus.we = 0
|
||||
else:
|
||||
selfp.bus.cyc = 0
|
||||
selfp.bus.stb = 0
|
||||
|
||||
|
||||
class TargetModel:
|
||||
def read(self, address):
|
||||
return 0
|
||||
|
||||
def write(self, address, data, sel):
|
||||
pass
|
||||
|
||||
def can_ack(self, bus):
|
||||
return True
|
||||
|
||||
|
||||
class Target(Module):
|
||||
def __init__(self, model, bus=None):
|
||||
if bus is None:
|
||||
bus = Interface()
|
||||
self.bus = bus
|
||||
self.model = model
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
bus = selfp.bus
|
||||
if not bus.ack:
|
||||
if self.model.can_ack(bus) and bus.cyc and bus.stb:
|
||||
if bus.we:
|
||||
self.model.write(bus.adr, bus.dat_w, bus.sel)
|
||||
else:
|
||||
bus.dat_r = self.model.read(bus.adr)
|
||||
bus.ack = 1
|
||||
else:
|
||||
bus.ack = 0
|
||||
do_simulation.passive = True
|
||||
|
||||
|
||||
class SRAM(Module):
|
||||
def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
|
||||
if bus is None:
|
||||
bus = Interface()
|
||||
self.bus = bus
|
||||
bus_data_width = flen(self.bus.dat_r)
|
||||
if isinstance(mem_or_size, Memory):
|
||||
assert(mem_or_size.width <= bus_data_width)
|
||||
self.mem = mem_or_size
|
||||
else:
|
||||
self.mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
|
||||
if read_only is None:
|
||||
if hasattr(self.mem, "bus_read_only"):
|
||||
read_only = self.mem.bus_read_only
|
||||
else:
|
||||
read_only = False
|
||||
|
||||
###
|
||||
|
||||
# memory
|
||||
port = self.mem.get_port(write_capable=not read_only, we_granularity=8)
|
||||
self.specials += self.mem, port
|
||||
# generate write enable signal
|
||||
if not read_only:
|
||||
self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
|
||||
for i in range(4)]
|
||||
# address and data
|
||||
self.comb += [
|
||||
port.adr.eq(self.bus.adr[:flen(port.adr)]),
|
||||
self.bus.dat_r.eq(port.dat_r)
|
||||
]
|
||||
if not read_only:
|
||||
self.comb += port.dat_w.eq(self.bus.dat_w),
|
||||
# generate ack
|
||||
self.sync += [
|
||||
self.bus.ack.eq(0),
|
||||
If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
|
||||
]
|
||||
|
||||
|
||||
class CSRBank(csr.GenericBank):
|
||||
def __init__(self, description, bus=None):
|
||||
if bus is None:
|
||||
bus = Interface()
|
||||
self.bus = bus
|
||||
|
||||
###
|
||||
|
||||
GenericBank.__init__(self, description, flen(self.bus.dat_w))
|
||||
|
||||
for i, c in enumerate(self.simple_csrs):
|
||||
self.comb += [
|
||||
c.r.eq(self.bus.dat_w[:c.size]),
|
||||
c.re.eq(self.bus.cyc & self.bus.stb & ~self.bus.ack & self.bus.we & \
|
||||
(self.bus.adr[:self.decode_bits] == i))
|
||||
]
|
||||
|
||||
brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(self.simple_csrs))
|
||||
self.sync += [
|
||||
Case(self.bus.adr[:self.decode_bits], brcases),
|
||||
If(bus.ack, bus.ack.eq(0)).Elif(bus.cyc & bus.stb, bus.ack.eq(1))
|
||||
]
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
from migen.fhdl.std import *
|
||||
from migen.bus import wishbone
|
||||
from migen.bus import csr
|
||||
from migen.genlib.misc import timeline
|
||||
|
||||
|
||||
class WB2CSR(Module):
|
||||
def __init__(self, bus_wishbone=None, bus_csr=None):
|
||||
if bus_wishbone is None:
|
||||
bus_wishbone = wishbone.Interface()
|
||||
self.wishbone = bus_wishbone
|
||||
if bus_csr is None:
|
||||
bus_csr = csr.Interface()
|
||||
self.csr = bus_csr
|
||||
|
||||
###
|
||||
|
||||
self.sync += [
|
||||
self.csr.we.eq(0),
|
||||
self.csr.dat_w.eq(self.wishbone.dat_w),
|
||||
self.csr.adr.eq(self.wishbone.adr),
|
||||
self.wishbone.dat_r.eq(self.csr.dat_r)
|
||||
]
|
||||
self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
|
||||
(1, [self.csr.we.eq(self.wishbone.we)]),
|
||||
(2, [self.wishbone.ack.eq(1)]),
|
||||
(3, [self.wishbone.ack.eq(0)])
|
||||
])
|
||||
Loading…
Reference in New Issue