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Use new verilog.convert API

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Sebastien Bourdeauducq 2012-01-20 23:00:11 +01:00
parent f8d5c27ef8
commit f6aa95a4d0
1 changed files with 2 additions and 3 deletions
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5
top.py
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@ -24,12 +24,11 @@ def get():
csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface]) csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
frag = autofragment.from_local() frag = autofragment.from_local()
vns = tools.Namespace() src_verilog, vns = verilog.convert(frag,
src_verilog = verilog.convert(frag,
{clkfx_sys.clkin, reset0.trigger_reset}, {clkfx_sys.clkin, reset0.trigger_reset},
name="soc", name="soc",
clk_signal=clkfx_sys.clkout, clk_signal=clkfx_sys.clkout,
rst_signal=reset0.sys_rst, rst_signal=reset0.sys_rst,
ns=vns) return_ns=True)
src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0) src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
return (src_verilog, src_ucf) return (src_verilog, src_ucf)