Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

Use new verilog.convert API

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2012-01-20 23:00:11 +01:00
parent f8d5c27ef8
commit f6aa95a4d0
1 changed files with 2 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
top.py
View file

@ -24,12 +24,11 @@ def get():
csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
frag = autofragment.from_local()
vns = tools.Namespace()
src_verilog = verilog.convert(frag,
src_verilog, vns = verilog.convert(frag,
{clkfx_sys.clkin, reset0.trigger_reset},
name="soc",
clk_signal=clkfx_sys.clkout,
rst_signal=reset0.sys_rst,
ns=vns)
return_ns=True)
src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
return (src_verilog, src_ucf)