Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/interconnect/stream: improve Pipeline to allow passing endpoints

This commit is contained in:
Florent Kermarrec 2015-11-28 18:31:47 +01:00
parent d85d2b7b9b
commit f6aeb6e41a
1 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
litex/soc/interconnect/stream.py
View File

@ -478,7 +478,16 @@ class Pipeline(Module):
self.sink = m.sink self.sink = m.sink
for i in range(1, n): for i in range(1, n):
m_n = modules[i] m_n = modules[i]
self.comb += m.source.connect(m_n.sink) if isinstance(m, _Endpoint):
source = m
else:
source = m.source
if isinstance(m_n, _Endpoint):
sink = m_n
else:
sink = m_n.sink
if m is not m_n:
self.comb += Record.connect(source, sink)
m = m_n m = m_n
# expose source of last module # expose source of last module
# if available # if available