soc/interconnect: add packet
This commit is contained in:
Florent Kermarrec
parent
525da89c7d
commit
f6b30fcae2
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@ -0,0 +1,381 @@
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from migen import *
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from migen.genlib.roundrobin import *
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from migen.genlib.record import *
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from migen.genlib.fsm import FSM, NextState
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from litex.soc.interconnect.stream import *
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# TODO: move reverse_bytes / Counter
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def reverse_bytes(signal):
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n = (flen(signal)+7)//8
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r = []
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for i in reversed(range(n)):
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r.append(signal[i*8:min((i+1)*8, flen(signal))])
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return Cat(iter(r))
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@ResetInserter()
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@CEInserter()
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class Counter(Module):
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def __init__(self, *args, increment=1, **kwargs):
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self.value = Signal(*args, **kwargs)
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self.width = flen(self.value)
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self.sync += self.value.eq(self.value+increment)
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class Status(Module):
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def __init__(self, endpoint):
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self.sop = sop = Signal()
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self.eop = eop =Signal()
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self.ongoing = Signal()
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ongoing = Signal()
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self.comb += \
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If(endpoint.stb,
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sop.eq(endpoint.sop),
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eop.eq(endpoint.eop & endpoint.ack)
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)
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self.sync += ongoing.eq((sop | ongoing) & ~eop)
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self.comb += self.ongoing.eq((sop | ongoing) & ~eop)
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class Arbiter(Module):
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def __init__(self, masters, slave):
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if len(masters) == 0:
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pass
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elif len(masters) == 1:
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self.grant = Signal()
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self.comb += Record.connect(masters.pop(), slave)
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else:
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self.submodules.rr = RoundRobin(len(masters))
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self.grant = self.rr.grant
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cases = {}
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for i, master in enumerate(masters):
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status = Status(master)
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self.submodules += status
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self.comb += self.rr.request[i].eq(status.ongoing)
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cases[i] = [Record.connect(master, slave)]
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self.comb += Case(self.grant, cases)
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class Dispatcher(Module):
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def __init__(self, master, slaves, one_hot=False):
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if len(slaves) == 0:
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self.sel = Signal()
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elif len(slaves) == 1:
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self.comb += Record.connect(master, slaves.pop())
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self.sel = Signal()
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else:
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if one_hot:
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self.sel = Signal(len(slaves))
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else:
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self.sel = Signal(max=len(slaves))
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# # #
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status = Status(master)
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self.submodules += status
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sel = Signal.like(self.sel)
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sel_ongoing = Signal.like(self.sel)
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self.sync += \
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If(status.sop,
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sel_ongoing.eq(self.sel)
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)
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self.comb += \
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If(status.sop,
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sel.eq(self.sel)
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).Else(
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sel.eq(sel_ongoing)
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)
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cases = {}
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for i, slave in enumerate(slaves):
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if one_hot:
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idx = 2**i
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else:
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idx = i
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cases[idx] = [Record.connect(master, slave)]
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cases["default"] = [master.ack.eq(1)]
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self.comb += Case(sel, cases)
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class HeaderField:
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def __init__(self, byte, offset, width):
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self.byte = byte
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self.offset = offset
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self.width = width
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class Header:
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def __init__(self, fields, length, swap_field_bytes=True):
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self.fields = fields
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self.length = length
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self.swap_field_bytes = swap_field_bytes
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def get_layout(self):
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layout = []
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for k, v in sorted(self.fields.items()):
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layout.append((k, v.width))
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return layout
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def get_field(self, obj, name, width):
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if "_lsb" in name:
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field = getattr(obj, name.replace("_lsb", ""))[:width]
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elif "_msb" in name:
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field = getattr(obj, name.replace("_msb", ""))[width:2*width]
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else:
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field = getattr(obj, name)
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return field
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def encode(self, obj, signal):
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r = []
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for k, v in sorted(self.fields.items()):
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start = v.byte*8+v.offset
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end = start+v.width
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field = self.get_field(obj, k, v.width)
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if self.swap_field_bytes:
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field = reverse_bytes(field)
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r.append(signal[start:end].eq(field))
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return r
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def decode(self, signal, obj):
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r = []
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for k, v in sorted(self.fields.items()):
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start = v.byte*8+v.offset
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end = start+v.width
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field = self.get_field(obj, k, v.width)
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if self.swap_field_bytes:
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r.append(field.eq(reverse_bytes(signal[start:end])))
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else:
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r.append(field.eq(signal[start:end]))
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return r
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class Packetizer(Module):
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def __init__(self, sink_description, source_description, header):
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self.sink = sink = Sink(sink_description)
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self.source = source = Source(source_description)
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self.header = Signal(header.length*8)
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# # #
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dw = flen(self.sink.data)
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header_reg = Signal(header.length*8)
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header_words = (header.length*8)//dw
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load = Signal()
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shift = Signal()
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counter = Counter(max=max(header_words, 2))
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self.submodules += counter
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self.comb += header.encode(sink, self.header)
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if header_words == 1:
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self.sync += [
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If(load,
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header_reg.eq(self.header)
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)
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]
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else:
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self.sync += [
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If(load,
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header_reg.eq(self.header)
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).Elif(shift,
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header_reg.eq(Cat(header_reg[dw:], Signal(dw)))
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)
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]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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if header_words == 1:
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idle_next_state = "COPY"
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else:
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idle_next_state = "SEND_HEADER"
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fsm.act("IDLE",
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sink.ack.eq(1),
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counter.reset.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(0),
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source.data.eq(self.header[:dw]),
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If(source.stb & source.ack,
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load.eq(1),
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NextState(idle_next_state)
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)
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)
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)
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if header_words != 1:
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fsm.act("SEND_HEADER",
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source.stb.eq(1),
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source.sop.eq(0),
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source.eop.eq(0),
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source.data.eq(header_reg[dw:2*dw]),
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If(source.stb & source.ack,
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shift.eq(1),
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counter.ce.eq(1),
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If(counter.value == header_words-2,
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NextState("COPY")
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)
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)
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)
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fsm.act("COPY",
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source.stb.eq(sink.stb),
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source.sop.eq(0),
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source.eop.eq(sink.eop),
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source.data.eq(sink.data),
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source.error.eq(sink.error),
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If(source.stb & source.ack,
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sink.ack.eq(1),
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If(source.eop,
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NextState("IDLE")
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)
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)
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)
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class Depacketizer(Module):
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def __init__(self, sink_description, source_description, header):
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self.sink = sink = Sink(sink_description)
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self.source = source = Source(source_description)
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self.header = Signal(header.length*8)
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# # #
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dw = flen(sink.data)
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header_words = (header.length*8)//dw
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shift = Signal()
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counter = Counter(max=max(header_words, 2))
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self.submodules += counter
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if header_words == 1:
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self.sync += \
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If(shift,
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self.header.eq(sink.data)
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)
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else:
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self.sync += \
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If(shift,
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self.header.eq(Cat(self.header[dw:], sink.data))
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)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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if header_words == 1:
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idle_next_state = "COPY"
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else:
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idle_next_state = "RECEIVE_HEADER"
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fsm.act("IDLE",
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sink.ack.eq(1),
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counter.reset.eq(1),
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If(sink.stb,
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shift.eq(1),
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NextState(idle_next_state)
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)
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)
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if header_words != 1:
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fsm.act("RECEIVE_HEADER",
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sink.ack.eq(1),
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If(sink.stb,
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counter.ce.eq(1),
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shift.eq(1),
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If(counter.value == header_words-2,
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NextState("COPY")
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)
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)
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)
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no_payload = Signal()
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self.sync += \
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If(fsm.before_entering("COPY"),
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source.sop.eq(1),
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no_payload.eq(sink.eop)
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).Elif(source.stb & source.ack,
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source.sop.eq(0)
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)
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if hasattr(sink, "error"):
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self.comb += source.error.eq(sink.error)
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self.comb += [
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source.eop.eq(sink.eop | no_payload),
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source.data.eq(sink.data),
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header.decode(self.header, source)
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]
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fsm.act("COPY",
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sink.ack.eq(source.ack),
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source.stb.eq(sink.stb | no_payload),
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If(source.stb & source.ack & source.eop,
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NextState("IDLE")
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)
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)
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class Buffer(Module):
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def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
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self.sink = sink = Sink(description)
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self.source = source = Source(description)
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# # #
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sink_status = Status(self.sink)
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source_status = Status(self.source)
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self.submodules += sink_status, source_status
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# store incoming packets
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# cmds
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def cmd_description():
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layout = [("error", 1)]
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return EndpointDescription(layout)
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cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
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self.submodules += cmd_fifo
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self.comb += cmd_fifo.sink.stb.eq(sink_status.eop)
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if hasattr(sink, "error"):
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self.comb += cmd_fifo.sink.error.eq(sink.error)
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# data
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data_fifo = SyncFIFO(description, data_depth, buffered=True)
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self.submodules += data_fifo
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self.comb += [
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Record.connect(self.sink, data_fifo.sink),
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data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack),
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self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack),
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]
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# output packets
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self.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(cmd_fifo.source.stb,
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NextState("SEEK_SOP")
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)
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)
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fsm.act("SEEK_SOP",
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If(~data_fifo.source.sop,
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data_fifo.source.ack.eq(1)
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).Else(
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NextState("OUTPUT")
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)
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)
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if hasattr(source, "error"):
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source_error = self.source.error
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else:
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source_error = Signal()
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fsm.act("OUTPUT",
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Record.connect(data_fifo.source, self.source),
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source_error.eq(cmd_fifo.source.error),
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If(source_status.eop,
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cmd_fifo.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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# compute almost full
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if almost_full is not None:
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self.almost_full = Signal()
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self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)
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