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software/liblitedram/sdram.c: Avoid direct ddrphy_wdly_dq_rst during DQ-DQS training on Ultrascale/Ultrascale+ (seems to cause issue on some configurations/modules). 

Also add a delay to be similar to read_leveling reset/inc functions.
This commit is contained in:
Florent Kermarrec 2021-04-28 14:41:54 +02:00
parent dc4f9772ba
commit f7b615ffab
1 changed files with 16 additions and 2 deletions
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18
litex/soc/software/liblitedram/sdram.c
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@ -512,10 +512,10 @@ static void sdram_write_leveling_rst_delay(int module) {
/* Select module */ /* Select module */
ddrphy_dly_sel_write(1 << module); ddrphy_dly_sel_write(1 << module);
#if defined(SDRAM_PHY_USDDRPHY) || defined(SDRAM_PHY_USPDDRPHY)
/* Reset DQ delay */ /* Reset DQ delay */
ddrphy_wdly_dq_rst_write(1); ddrphy_wdly_dq_rst_write(1);
#if defined(SDRAM_PHY_USDDRPHY) || defined(SDRAM_PHY_USPDDRPHY)
/* Reset DQS delay */ /* Reset DQS delay */
while (ddrphy_wdly_dqs_inc_count_read() != 0) { while (ddrphy_wdly_dqs_inc_count_read() != 0) {
ddrphy_wdly_dqs_inc_write(1); ddrphy_wdly_dqs_inc_write(1);
@ -1029,8 +1029,21 @@ static void sdram_write_latency_calibration(void) {
static void sdram_write_dq_dqs_training_rst_delay(int module) { static void sdram_write_dq_dqs_training_rst_delay(int module) {
/* Select module */ /* Select module */
ddrphy_dly_sel_write(1 << module); ddrphy_dly_sel_write(1 << module);
/* Reset delay */
#if defined(SDRAM_PHY_USDDRPHY) || defined(SDRAM_PHY_USPDDRPHY)
/* Reset DQ delay */
int dq_count = ddrphy_wdly_dqs_inc_count_read();
while (dq_count != SDRAM_PHY_DELAYS) {
ddrphy_wdly_dq_inc_write(1);
cdelay(100);
dq_count++;
}
#else
/* Reset DQ delay */
ddrphy_wdly_dq_rst_write(1); ddrphy_wdly_dq_rst_write(1);
cdelay(100);
#endif
/* Un-select module */ /* Un-select module */
ddrphy_dly_sel_write(0); ddrphy_dly_sel_write(0);
} }
@ -1040,6 +1053,7 @@ static void sdram_write_dq_dqs_training_inc_delay(int module) {
ddrphy_dly_sel_write(1 << module); ddrphy_dly_sel_write(1 << module);
/* Increment delay */ /* Increment delay */
ddrphy_wdly_dq_inc_write(1); ddrphy_wdly_dq_inc_write(1);
cdelay(100);
/* Un-select module */ /* Un-select module */
ddrphy_dly_sel_write(0); ddrphy_dly_sel_write(0);
} }