interconnect/axi: Add 8-bit/16-bit data-widths.

2022-10-18 14:15:08 +02:00 · 2022-10-18 14:15:08 +02:00 · f7e05b1953
parent 838a30f148
commit f7e05b1953
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/interconnect/axi/axi_full.py
+++ b/litex/soc/interconnect/axi/axi_full.py
@ -61,7 +61,7 @@ class AXIInterface:
    ):
        # Parameters checks.
        # ------------------
-        assert data_width in [32, 64, 128, 256, 512, 1024]
+        assert data_width in [8, 16, 32, 64, 128, 256, 512, 1024]
        assert version    in ["axi3", "axi4"]
        # Parameters.