gen/common/LiteXModule: Also inherit from AutoDoc.
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@ -9,6 +9,8 @@ from migen.fhdl.module import _ModuleProxy
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from migen.fhdl.specials import Special
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from migen.fhdl.specials import Special
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from litex.soc.interconnect.csr import AutoCSR
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from litex.soc.interconnect.csr import AutoCSR
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from litex.soc.integration.doc import AutoDoc
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# Bit/Bytes Reversing ------------------------------------------------------------------------------
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# Bit/Bytes Reversing ------------------------------------------------------------------------------
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@ -23,7 +25,7 @@ def reverse_bytes(s):
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# LiteX Module -------------------------------------------------------------------------------------
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# LiteX Module -------------------------------------------------------------------------------------
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class LiteXModule(Module, AutoCSR):
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class LiteXModule(Module, AutoCSR, AutoDoc):
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def __setattr__(m, name, value):
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def __setattr__(m, name, value):
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# Migen:
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# Migen:
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if name in ["comb", "sync", "specials", "submodules", "clock_domains"]:
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if name in ["comb", "sync", "specials", "submodules", "clock_domains"]:
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