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stream/ClockDomainCrossing: Make common reset an option (Enabled by default).

This commit is contained in:
Florent Kermarrec 2022-03-29 17:07:20 +02:00
parent 38a7b1fee0
commit f944b656d5
1 changed files with 22 additions and 18 deletions
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12
litex/soc/interconnect/stream.py
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@ -242,7 +242,7 @@ class AsyncFIFO(_FIFOWrapper):
# ClockDomainCrossing ------------------------------------------------------------------------------ # ClockDomainCrossing ------------------------------------------------------------------------------
class ClockDomainCrossing(Module): class ClockDomainCrossing(Module):
def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None): def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, with_common_rst=True):
self.sink = Endpoint(layout) self.sink = Endpoint(layout)
self.source = Endpoint(layout) self.source = Endpoint(layout)
# # # # # #
@ -253,6 +253,7 @@ class ClockDomainCrossing(Module):
self.comb += self.sink.connect(self.source) self.comb += self.sink.connect(self.source)
# Different Clk Domains. # Different Clk Domains.
else: else:
if with_common_rst:
# Create intermediate Clk Domains and generate a common Rst. # Create intermediate Clk Domains and generate a common Rst.
_cd_rst = Signal() _cd_rst = Signal()
_cd_from = ClockDomain("from") _cd_from = ClockDomain("from")
@ -263,14 +264,17 @@ class ClockDomainCrossing(Module):
_cd_to.clk.eq( ClockSignal(cd_to)), _cd_to.clk.eq( ClockSignal(cd_to)),
_cd_rst.eq(ResetSignal(cd_from) | ResetSignal(cd_to)) _cd_rst.eq(ResetSignal(cd_from) | ResetSignal(cd_to))
] ]
cd_from = "from"
cd_to = "to"
# Use common Rst on both Clk Domains (through AsyncResetSynchronizer). # Use common Rst on both Clk Domains (through AsyncResetSynchronizer).
self.specials += [ self.specials += [
AsyncResetSynchronizer(_cd_from, _cd_rst), AsyncResetSynchronizer(_cd_from, _cd_rst),
AsyncResetSynchronizer(_cd_to, _cd_rst) AsyncResetSynchronizer(_cd_to, _cd_rst),
] ]
# Add Asynchronous FIFO (with intermediate Clk Domains).
# Add Asynchronous FIFO
cdc = AsyncFIFO(layout, depth) cdc = AsyncFIFO(layout, depth)
cdc = ClockDomainsRenamer({"write": "from", "read": "to"})(cdc) cdc = ClockDomainsRenamer({"write": cd_from, "read": cd_to})(cdc)
self.submodules += cdc self.submodules += cdc
# Sink -> AsyncFIFO -> Source. # Sink -> AsyncFIFO -> Source.