stream/ClockDomainCrossing: Make common reset an option (Enabled by default).
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38a7b1fee0
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@ -242,7 +242,7 @@ class AsyncFIFO(_FIFOWrapper):
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# ClockDomainCrossing ------------------------------------------------------------------------------
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# ClockDomainCrossing ------------------------------------------------------------------------------
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class ClockDomainCrossing(Module):
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class ClockDomainCrossing(Module):
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def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None):
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def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, with_common_rst=True):
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self.sink = Endpoint(layout)
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self.sink = Endpoint(layout)
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self.source = Endpoint(layout)
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self.source = Endpoint(layout)
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# # #
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# # #
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@ -253,24 +253,28 @@ class ClockDomainCrossing(Module):
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self.comb += self.sink.connect(self.source)
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self.comb += self.sink.connect(self.source)
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# Different Clk Domains.
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# Different Clk Domains.
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else:
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else:
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# Create intermediate Clk Domains and generate a common Rst.
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if with_common_rst:
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_cd_rst = Signal()
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# Create intermediate Clk Domains and generate a common Rst.
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_cd_from = ClockDomain("from")
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_cd_rst = Signal()
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_cd_to = ClockDomain("to")
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_cd_from = ClockDomain("from")
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self.clock_domains += _cd_from, _cd_to
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_cd_to = ClockDomain("to")
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self.comb += [
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self.clock_domains += _cd_from, _cd_to
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_cd_from.clk.eq(ClockSignal(cd_from)),
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self.comb += [
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_cd_to.clk.eq( ClockSignal(cd_to)),
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_cd_from.clk.eq(ClockSignal(cd_from)),
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_cd_rst.eq(ResetSignal(cd_from) | ResetSignal(cd_to))
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_cd_to.clk.eq( ClockSignal(cd_to)),
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]
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_cd_rst.eq(ResetSignal(cd_from) | ResetSignal(cd_to))
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# Use common Rst on both Clk Domains (through AsyncResetSynchronizer).
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]
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self.specials += [
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cd_from = "from"
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AsyncResetSynchronizer(_cd_from, _cd_rst),
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cd_to = "to"
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AsyncResetSynchronizer(_cd_to, _cd_rst)
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# Use common Rst on both Clk Domains (through AsyncResetSynchronizer).
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]
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self.specials += [
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# Add Asynchronous FIFO (with intermediate Clk Domains).
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AsyncResetSynchronizer(_cd_from, _cd_rst),
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AsyncResetSynchronizer(_cd_to, _cd_rst),
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]
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# Add Asynchronous FIFO
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cdc = AsyncFIFO(layout, depth)
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cdc = AsyncFIFO(layout, depth)
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cdc = ClockDomainsRenamer({"write": "from", "read": "to"})(cdc)
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cdc = ClockDomainsRenamer({"write": cd_from, "read": cd_to})(cdc)
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self.submodules += cdc
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self.submodules += cdc
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# Sink -> AsyncFIFO -> Source.
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# Sink -> AsyncFIFO -> Source.
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