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This commit is contained in:
Sebastien Bourdeauducq 2015-09-10 20:32:47 -07:00
parent 714ae43ab8
commit f9849fb8be
1 changed files with 4 additions and 1 deletions
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5
migen/fhdl/verilog.py
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@ -8,6 +8,7 @@ from migen.fhdl.bitcontainer import bits_for, flen
from migen.fhdl.namer import Namespace, build_namespace from migen.fhdl.namer import Namespace, build_namespace
from migen.fhdl.conv_output import ConvOutput from migen.fhdl.conv_output import ConvOutput
_reserved_keywords = { _reserved_keywords = {
"always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1", "always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1",
"case", "casex", "casez", "cell", "cmos", "config", "deassign", "default", "case", "casex", "casez", "cell", "cmos", "config", "deassign", "default",
@ -25,7 +26,8 @@ _reserved_keywords = {
"specparam", "strong0", "strong1", "supply0", "supply1", "table", "task", "specparam", "strong0", "strong1", "supply0", "supply1", "table", "task",
"time", "tran", "tranif0", "tranif1", "tri", "tri0", "tri1", "triand", "time", "tran", "tranif0", "tranif1", "tri", "tri0", "tri1", "triand",
"trior", "trireg", "unsigned", "use", "vectored", "wait", "wand", "weak0", "trior", "trireg", "unsigned", "use", "vectored", "wait", "wand", "weak0",
"weak1", "while", "wire", "wor","xnor","xor"} "weak1", "while", "wire", "wor","xnor","xor"
}
def _printsig(ns, s): def _printsig(ns, s):
@ -116,6 +118,7 @@ def _printexpr(ns, node):
else: else:
raise TypeError("Expression of unrecognized type: "+str(type(node))) raise TypeError("Expression of unrecognized type: "+str(type(node)))
(_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3) (_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)