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soc/cores/clock: improve presentation

This commit is contained in:
Florent Kermarrec 2019-04-15 10:57:00 +02:00
parent 538ca59ab6
commit f986974d60
1 changed files with 4 additions and 9 deletions
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13
litex/soc/cores/clock.py
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@ -1,9 +1,4 @@
""" """Clock Abstraction Modules"""
Clock Abstraction Modules
Made in Paris-CDG while waiting a delayed Air-France KLM flight...
"""
from migen import * from migen import *
from migen.genlib.io import DifferentialInput from migen.genlib.io import DifferentialInput
@ -15,7 +10,7 @@ from litex.soc.interconnect.csr import *
def period_ns(freq): def period_ns(freq):
return 1e9/freq return 1e9/freq
# Xilinx / 7-Series # Xilinx / 7-Series --------------------------------------------------------------------------------
class S7Clocking(Module, AutoCSR): class S7Clocking(Module, AutoCSR):
clkfbout_mult_frange = (2, 64+1) clkfbout_mult_frange = (2, 64+1)
@ -204,7 +199,7 @@ class S7IDELAYCTRL(Module):
) )
self.specials += Instance("IDELAYCTRL", i_REFCLK=cd.clk, i_RST=ic_reset) self.specials += Instance("IDELAYCTRL", i_REFCLK=cd.clk, i_RST=ic_reset)
# Xilinx / Ultrascale # Xilinx / Ultrascale ------------------------------------------------------------------------------
# TODO: # TODO:
# - use Ultrascale primitives instead of 7-Series' ones. (Vivado recognize and convert them). # - use Ultrascale primitives instead of 7-Series' ones. (Vivado recognize and convert them).
@ -404,7 +399,7 @@ class USIDELAYCTRL(Module):
i_REFCLK=cd.clk, i_REFCLK=cd.clk,
i_RST=ic_reset) i_RST=ic_reset)
# Lattice / ECP5 # Lattice / ECP5 -----------------------------------------------------------------------------------
# TODO: # TODO:
# - add proper phase support. # - add proper phase support.