arp: request/reply with model OK
This commit is contained in:
Florent Kermarrec
parent
a7d4427de4
commit
fa48346385
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@ -80,7 +80,7 @@ class LiteEthARPTX(Module):
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self.source.source_mac_address.eq(mac_address),
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self.source.ethernet_type.eq(ethernet_type_arp),
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If(self.source.stb & self.source.ack,
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sink.ack.eq(1),
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sink.ack.eq(source.eop),
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counter.ce.eq(1),
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If(self.source.eop,
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NextState("IDLE")
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@ -148,7 +148,6 @@ arp_table_request_layout = [
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arp_table_response_layout = [
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("failed", 1),
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("mac_address", 48)
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]
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class LiteEthARPTable(Module):
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@ -159,15 +158,31 @@ class LiteEthARPTable(Module):
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# Request/Response interface
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self.request = request = Sink(arp_table_request_layout)
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self.response = response = Source(arp_table_response_layout)
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###
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request_timeout = Timeout(512) # XXX fix me 100ms?
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request_pending = FlipFlop()
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self.submodules += request_timeout, request_pending
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self.comb += [
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request_timeout.ce.eq(request_pending.q),
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request_pending.d.eq(1)
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]
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# Note: Store only one ip/mac couple, replace this with
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# a real ARP table
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update = Signal()
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cached_ip_address = Signal(32)
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cached_mac_address = Signal(48)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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# Note: for simplicicy, if APR table is busy response from arp_rx
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# is lost. This is compensated by the protocol (retrys)
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If(sink.stb & sink.request,
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NextState("SEND_REPLY")
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).Elif(sink.stb & sink.reply,
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).Elif(sink.stb & sink.reply & request_pending.q,
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NextState("UPDATE_TABLE")
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).Elif(request.stb,
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).Elif(request.stb | (request_pending.q & request_timeout.reached),
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NextState("CHECK_TABLE")
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)
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)
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@ -180,13 +195,21 @@ class LiteEthARPTable(Module):
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)
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)
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fsm.act("UPDATE_TABLE",
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# XXX update memory
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NextState("IDLE")
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request_pending.reset.eq(1),
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update.eq(1),
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NextState("CHECK_TABLE")
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)
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self.sync += [
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If(update,
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cached_ip_address.eq(sink.ip_address),
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cached_mac_address.eq(sink.mac_address)
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)
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]
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found = Signal()
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fsm.act("CHECK_TABLE",
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# XXX add a kind of CAM?
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If(found,
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# XXX: add a live time for cached_mac_address
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If(request.ip_address == cached_ip_address,
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request.ack.eq(request.stb),
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NextState("PRESENT_RESPONSE")
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).Else(
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NextState("SEND_REQUEST")
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@ -197,13 +220,16 @@ class LiteEthARPTable(Module):
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source.request.eq(1),
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source.ip_address.eq(request.ip_address),
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If(source.ack,
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request_timeout.reset.eq(1),
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request_pending.ce.eq(1),
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request.ack.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("PRESENT_RESPONSE",
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response.stb.eq(1),
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response.failed.eq(0), # XXX add timeout to trigger failed
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response.mac_address.eq(0x12345678abcd), # XXX get mac address from table
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response.mac_address.eq(cached_mac_address),
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If(response.ack,
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NextState("IDLE")
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)
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@ -129,6 +129,14 @@ def eth_udp_description(dw):
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return EndpointDescription(layout, packetized=True)
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# Generic modules
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class FlipFlop(Module):
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def __init__(self, **kwargs):
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self.d = Signal(**kwargs)
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self.q = Signal(**kwargs)
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self.sync += self.q.eq(self.d)
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class Counter(Module):
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@ -147,8 +155,8 @@ class Timeout(Module):
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self.reached = Signal()
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###
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value = Signal(max=length)
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self.sync += value.eq(value+1)
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self.comb += self.reached.eq(value == length)
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self.sync += If(~self.reached, value.eq(value+1))
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self.comb += self.reached.eq(value == (length-1))
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class BufferizeEndpoints(ModuleDecorator):
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def __init__(self, submodule, *args):
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@ -18,11 +18,10 @@ class LiteEthDepacketizer(Module):
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counter = Counter(max=header_length)
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self.submodules += counter
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self.sync += [
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self.sync += \
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If(shift,
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header.eq(Cat(header[8:], sink.data))
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)
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]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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@ -47,8 +47,15 @@ class TB(Module):
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for i in range(100):
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yield
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selfp.arp.table.request.ip_address = 0x12345678
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selfp.arp.table.request.stb = 1
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while selfp.arp.table.request.ack != 1:
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selfp.arp.table.request.stb = 1
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selfp.arp.table.request.ip_address = 0x12345678
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yield
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selfp.arp.table.request.stb = 0
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while selfp.arp.table.response.stb != 1:
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selfp.arp.table.response.ack = 1
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yield
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)
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run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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