fhdl: replication support

migen/fhdl/convtools.py

@@ -37,6 +37,8 @@ def ListSignals(node):
 	elif isinstance(node, Cat):
 		l = list(map(ListSignals, node.l))
 		return set().union(*l)
+	elif isinstance(node, Replicate):
+		return ListSignals(node.v)
 	elif isinstance(node, Assign):
 		return ListSignals(node.l) | ListSignals(node.r)
 	elif isinstance(node, StatementList):
@@ -60,6 +62,8 @@ def ListTargets(node):
 	elif isinstance(node, Cat):
 		l = list(map(ListTargets, node.l))
 		return set().union(*l)
+	elif isinstance(node, Replicate):
+		return ListTargets(node.v)
 	elif isinstance(node, Assign):
 		return ListTargets(node.l)
 	elif isinstance(node, StatementList):

migen/fhdl/structure.py

@@ -1,6 +1,9 @@
 import math
 
 def BitsFor(n):
+	if isinstance(n, Constant):
+		return n.bv.width
+	else:
 		if n == 0:
 			return 1
 		else:
@@ -11,7 +14,7 @@ class BV:
 		self.width = width
 		self.signed = signed
 	
-	def __str__(self):
+	def __repr__(self):
 		r = str(self.width) + "'"
 		if self.signed:
 			r += "s"
@@ -98,11 +101,19 @@ class Cat(Value):
 	def __init__(self, *args):
 		self.l = list(map(_cst, args))
 
+class Replicate(Value):
+	def __init__(self, v, n):
+		self.v = v
+		self.n = n
+
 class Constant(Value):
 	def __init__(self, n, bv=None):
 		self.bv = bv or BV(BitsFor(n))
 		self.n = n
 	
+	def __repr__(self):
+		return str(self.bv) + str(self.n)
+
 def _cst(x):
 	if isinstance(x, int):
 		return Constant(x)

migen/fhdl/verilog.py

@@ -39,6 +39,8 @@ def _printexpr(ns, node):
 		l = list(map(partial(_printexpr, ns), node.l))
 		l.reverse()
 		return "{" + ", ".join(l) + "}"
+	elif isinstance(node, Replicate):
+		return "{" + str(node.n) + "{" + _printexpr(ns, node.v) + "}}"
 	else:
 		raise TypeError