soc/cores/hyperbus: Full rewrite of HyperRAM core.
Rewriting the HyperRAM core to improve its design and functionality. The old core grew complex over time without a clear structure. This new version offers: - IO registers on all signals for better performance. - Flexible clocking options. - Simplified architecture. - Easier to extend with new features. This rewrite provides a base for future development.
This commit is contained in:
Florent Kermarrec
parent
ef775e0b8e
commit
fac80c3a51
File diff suppressed because it is too large
Load Diff
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@ -18,7 +18,7 @@ static void hyperram_write_reg(uint16_t reg_addr, uint16_t data) {
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reg_addr << CSR_HYPERRAM_REG_CONTROL_ADDR_OFFSET
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);
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/* Wait for write to complete */
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while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_WRITE_DONE_OFFSET)) == 0);
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while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_DONE_OFFSET)) == 0);
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}
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static uint16_t hyperram_read_reg(uint16_t reg_addr) {
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@ -29,7 +29,7 @@ static uint16_t hyperram_read_reg(uint16_t reg_addr) {
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reg_addr << CSR_HYPERRAM_REG_CONTROL_ADDR_OFFSET
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);
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/* Wait for read to complete */
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while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
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while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_DONE_OFFSET)) == 0);
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return hyperram_reg_rdata_read();
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}
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@ -55,41 +55,59 @@ static uint16_t hyperram_get_chip_latency_setting(uint32_t clk_freq) {
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return 0b0010; /* Default to highest latency for safety */
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}
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static void hyperram_configure_latency(void) {
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uint16_t config_reg_0 = 0x8f2f;
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void hyperram_init(void) {
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uint16_t config_reg_0;
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uint8_t core_clk_ratio;
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uint8_t core_latency_mode;
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uint16_t core_latency_setting;
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uint16_t chip_latency_setting;
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printf("HyperRAM init...\n");
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/* Compute Latency settings */
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core_clk_ratio = (hyperram_status_read() >> CSR_HYPERRAM_STATUS_CLK_RATIO_OFFSET & 0xf);
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printf("HyperRAM Clk Ratio %d:1.\n", core_clk_ratio);
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core_clk_ratio = (hyperram_status_read() >> CSR_HYPERRAM_STATUS_CLK_RATIO_OFFSET) & 0xf;
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printf("HyperRAM Clk Ratio %d:1\n", core_clk_ratio);
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core_latency_setting = hyperram_get_core_latency_setting(CONFIG_CLOCK_FREQUENCY / core_clk_ratio);
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chip_latency_setting = hyperram_get_chip_latency_setting(CONFIG_CLOCK_FREQUENCY / core_clk_ratio);
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/* Write Latency to HyperRAM Core */
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printf("HyperRAM Core Latency: %d CK (X1).\n", core_latency_setting);
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/* Configure Latency on HyperRAM Core */
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core_latency_mode = (hyperram_status_read() >> CSR_HYPERRAM_STATUS_LATENCY_MODE_OFFSET) & 0b1;
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printf("HyperRAM %s Latency: %d CK (X1)\n", (core_latency_mode == 0) ? "Fixed" : "Variable", core_latency_setting);
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hyperram_config_write(core_latency_setting << CSR_HYPERRAM_CONFIG_LATENCY_OFFSET);
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/* Configure HyperRAM Chip */
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config_reg_0 = (
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/* Burst Length */
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(HYPERRAM_CONFIG_0_REG_BL_32_BYTES << HYPERRAM_CONFIG_0_REG_BL_OFFSET) |
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/* Hybrid Burst Enable */
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(HYPERRAM_CONFIG_0_REG_HBE_LEGACY << HYPERRAM_CONFIG_0_REG_HBE_OFFSET) |
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/* Initial Latency */
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(chip_latency_setting << HYPERRAM_CONFIG_0_REG_IL_OFFSET) |
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/* Fixed Latency Enable */
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(HYPERRAM_CONFIG_0_REG_FLE_ENABLED << HYPERRAM_CONFIG_0_REG_FLE_OFFSET) |
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/* Reserved Bits (Set to 1 for future compatibility) */
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(0b1111 << HYPERRAM_CONFIG_0_REG_RSD_OFFSET) |
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/* Drive Strength */
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(HYPERRAM_CONFIG_0_REG_DS_19_OHM << HYPERRAM_CONFIG_0_REG_DS_OFFSET) |
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/* Deep Power Down: Normal operation */
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(HYPERRAM_CONFIG_0_REG_DPD_DISABLED << HYPERRAM_CONFIG_0_REG_DPD_OFFSET)
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);
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/* Enable Variable Latency on HyperRAM Chip */
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if (hyperram_status_read() & 0x1)
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config_reg_0 &= ~(0b1 << 3); /* Enable Variable Latency */
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/* Update Latency on HyperRAM Chip */
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config_reg_0 &= ~(0b1111 << 4);
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config_reg_0 |= chip_latency_setting << 4;
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/* Write Configuration Register 0 to HyperRAM Chip */
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hyperram_write_reg(2, config_reg_0);
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/* Read current configuration */
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config_reg_0 = hyperram_read_reg(2);
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printf("HyperRAM Configuration Register 0: %08x\n", config_reg_0);
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if (hyperram_status_read() & 0x1) {
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config_reg_0 &= ~(1 << HYPERRAM_CONFIG_0_REG_FLE_OFFSET);
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config_reg_0 |= (HYPERRAM_CONFIG_0_REG_FLE_DISABLED << HYPERRAM_CONFIG_0_REG_FLE_OFFSET);
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}
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hyperram_write_reg(HYPERRAM_CONFIG_0_REG, config_reg_0);
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void hyperram_init(void) {
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printf("HyperRAM init...\n");
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hyperram_configure_latency();
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/* Read current configuration to verify changes */
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config_reg_0 = hyperram_read_reg(HYPERRAM_CONFIG_0_REG);
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printf("HyperRAM Configuration Register 0: %04x\n", config_reg_0);
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printf("\n");
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}
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@ -8,6 +8,57 @@
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extern "C" {
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#endif
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/* HyperRAM Registers */
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#define HYPERRAM_ID_0_REG 0x0 /* Identification Register 0 */
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#define HYPERRAM_ID_1_REG 0x1 /* Identification Register 1 */
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#define HYPERRAM_CONFIG_0_REG 0x2 /* Configuration Register 0 */
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#define HYPERRAM_CONFIG_1_REG 0x3 /* Configuration Register 1 */
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/* Configuration Register 0 Field Offsets */
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#define HYPERRAM_CONFIG_0_REG_BL_OFFSET 0 /* Burst Length */
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#define HYPERRAM_CONFIG_0_REG_HBE_OFFSET 2 /* Hybrid Burst Enable */
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#define HYPERRAM_CONFIG_0_REG_FLE_OFFSET 3 /* Fixed Latency Enable */
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#define HYPERRAM_CONFIG_0_REG_IL_OFFSET 4 /* Initial Latency */
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#define HYPERRAM_CONFIG_0_REG_RSD_OFFSET 8 /* Reserved bits */
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#define HYPERRAM_CONFIG_0_REG_DS_OFFSET 12 /* Drive Strength */
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#define HYPERRAM_CONFIG_0_REG_DPD_OFFSET 15 /* Deep Power Down */
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/* Configuration Register 0 Field Values */
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/* Burst Length */
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#define HYPERRAM_CONFIG_0_REG_BL_128_BYTES 0b00
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#define HYPERRAM_CONFIG_0_REG_BL_64_BYTES 0b01
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#define HYPERRAM_CONFIG_0_REG_BL_16_BYTES 0b10
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#define HYPERRAM_CONFIG_0_REG_BL_32_BYTES 0b11
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/* Hybrid Burst Enable */
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#define HYPERRAM_CONFIG_0_REG_HBE_WRAPPED 0b0
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#define HYPERRAM_CONFIG_0_REG_HBE_LEGACY 0b1
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/* Fixed Latency Enable */
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#define HYPERRAM_CONFIG_0_REG_FLE_DISABLED 0b0
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#define HYPERRAM_CONFIG_0_REG_FLE_ENABLED 0b1
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/* Initial Latency */
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#define HYPERRAM_CONFIG_0_REG_IL_3_CLOCKS 0b1110
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#define HYPERRAM_CONFIG_0_REG_IL_4_CLOCKS 0b1111
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#define HYPERRAM_CONFIG_0_REG_IL_5_CLOCKS 0b0000
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#define HYPERRAM_CONFIG_0_REG_IL_6_CLOCKS 0b0001
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#define HYPERRAM_CONFIG_0_REG_IL_7_CLOCKS 0b0010
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/* Drive Strength */
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#define HYPERRAM_CONFIG_0_REG_DS_34_OHM 0b000
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#define HYPERRAM_CONFIG_0_REG_DS_115_OHM 0b001
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#define HYPERRAM_CONFIG_0_REG_DS_67_OHM 0b010
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#define HYPERRAM_CONFIG_0_REG_DS_46_OHM 0b011
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#define HYPERRAM_CONFIG_0_REG_DS_27_OHM 0b101
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#define HYPERRAM_CONFIG_0_REG_DS_22_OHM 0b110
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#define HYPERRAM_CONFIG_0_REG_DS_19_OHM 0b111
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/* Deep Power Down */
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#define HYPERRAM_CONFIG_0_REG_DPD_DISABLED 0b1
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#define HYPERRAM_CONFIG_0_REG_DPD_ENABLED 0b0
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void hyperram_init(void);
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#ifdef __cplusplus
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@ -1,7 +1,8 @@
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#
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# This file is part of LiteHyperBus
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# This file is part of LiteX
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#
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# Copyright (c) 2019-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2019-2024 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2024 MoTeC <www.motec.com.au>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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@ -16,21 +17,20 @@ def c2bool(c):
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class Pads: pass
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class HyperRamPads:
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def __init__(self, dw=8):
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self.clk = Signal()
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self.rst_n = Signal()
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self.cs_n = Signal()
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self.dq = Record([("oe", 1), ("o", dw), ("i", dw)])
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self.rwds = Record([("oe", 1), ("o", dw//8), ("i", dw//8)])
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class TestHyperBus(unittest.TestCase):
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class TestHyperRAM(unittest.TestCase):
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def test_hyperram_syntax(self):
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pads = Record([("clk", 1), ("cs_n", 1), ("dq", 8), ("rwds", 1)])
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pads = Record([("clk", 1), ("rst_n", 1), ("cs_n", 1), ("dq", 8), ("rwds", 1)])
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hyperram = HyperRAM(pads)
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pads = Record([("clk_p", 1), ("clk_n", 1), ("cs_n", 1), ("dq", 8), ("rwds", 1)])
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pads = Record([("clk_p", 1), ("clk_n", 1), ("rst_n", 1), ("cs_n", 1), ("dq", 8), ("rwds", 1)])
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hyperram = HyperRAM(pads)
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def test_hyperram_write_latency_5_2x(self):
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@ -39,12 +39,13 @@ class TestHyperBus(unittest.TestCase):
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yield
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "--________________________________________________________------"
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dq_oe = "__------------____________________________________--------______"
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dq_o = "002000048d0000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "__________________________________________________--------______"
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rwds_o = "____________________________________________________----________"
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "----__________________________________________________________------"
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dq_oe = "______------------____________________________________--------______"
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dq_o = "0000002000048d0000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "______________________________________________________--------______"
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rwds_o = "________________________________________________________----________"
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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@ -55,7 +56,7 @@ class TestHyperBus(unittest.TestCase):
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed")
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dut = HyperRAM(HyperRamPads(dw=8), latency=5, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_write_latency_5_2x_sys2x(self):
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@ -64,12 +65,12 @@ class TestHyperBus(unittest.TestCase):
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yield
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def hyperram_gen(dut):
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clk = "____--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "--________________________________________________________-------"
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dq_oe = "___------------____________________________________--------______"
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dq_o = "0002000048d0000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "___________________________________________________--------______"
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rwds_o = "_____________________________________________________----________"
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clk = "________________--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "_------------__________________________________________________________------"
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dq_oe = "_______________------------____________________________________--------______"
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dq_o = "0000000000000002000048d0000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "_______________________________________________________________--------______"
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rwds_o = "_________________________________________________________________----________"
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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@ -79,6 +80,8 @@ class TestHyperBus(unittest.TestCase):
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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for i in range(128):
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yield
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dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed", clk_ratio="2:1")
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generators = {
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@ -97,12 +100,13 @@ class TestHyperBus(unittest.TestCase):
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yield
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "--________________________________________________________________------"
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dq_oe = "__------------____________________________________________--------______"
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dq_o = "002000048d000000000000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "__________________________________________________________--------______"
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rwds_o = "____________________________________________________________----________"
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "----__________________________________________________________________------"
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dq_oe = "______------------____________________________________________--------______"
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dq_o = "0000002000048d000000000000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "______________________________________________________________--------______"
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rwds_o = "________________________________________________________________----________"
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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@ -122,12 +126,13 @@ class TestHyperBus(unittest.TestCase):
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yield
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "--________________________________________________________________________------"
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dq_oe = "__------------____________________________________________________--------______"
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dq_o = "002000048d00000000000000000000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "__________________________________________________________________--------______"
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rwds_o = "____________________________________________________________________----________"
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "----__________________________________________________________________________------"
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dq_oe = "______------------____________________________________________________--------______"
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dq_o = "0000002000048d00000000000000000000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "______________________________________________________________________--------______"
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rwds_o = "________________________________________________________________________----________"
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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@ -147,12 +152,13 @@ class TestHyperBus(unittest.TestCase):
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yield
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "--____________________________________________------"
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dq_oe = "__------------________________________--------______"
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dq_o = "002000048d0000000000000000000000000000deadbeef000000"
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rwds_oe = "______________________________________--------______"
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rwds_o = "________________________________________----________"
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clk = "_______--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "----______________________________________________------"
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dq_oe = "______------------________________________--------______"
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dq_o = "0000002000048d0000000000000000000000000000deadbeef000000"
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rwds_oe = "__________________________________________--------______"
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rwds_o = "____________________________________________----________"
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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@ -170,18 +176,19 @@ class TestHyperBus(unittest.TestCase):
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def fpga_gen(dut):
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dat = yield from dut.bus.read(0x1234)
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self.assertEqual(dat, 0xdeadbeef)
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dat = yield from dut.bus.read(0x1235)
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self.assertEqual(dat, 0xcafefade)
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
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cs_n = "--________________________________________________________________________"
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dq_oe = "__------------____________________________________________________________"
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dq_o = "00a000048d0000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "00000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
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rwds_oe = "__________________________________________________________________________"
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_____"
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cs_n = "----______________________________________________________________________----"
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dq_oe = "______------------____________________________________________________________"
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dq_o = "000000a000048d0000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
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rwds_oe = "______________________________________________________________________________"
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rwds_i = "______________________________________________________--__--__--__--__________"
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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yield dut.pads.rwds.i.eq(c2bool(rwds_i[i]))
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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@ -197,18 +204,19 @@ class TestHyperBus(unittest.TestCase):
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def fpga_gen(dut):
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dat = yield from dut.bus.read(0x1234)
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self.assertEqual(dat, 0xdeadbeef)
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dat = yield from dut.bus.read(0x1235)
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self.assertEqual(dat, 0xcafefade)
|
||||
|
||||
def hyperram_gen(dut):
|
||||
clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
|
||||
cs_n = "--________________________________________________________________________________"
|
||||
dq_oe = "__------------____________________________________________________________________"
|
||||
dq_o = "00a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
|
||||
dq_i = "0000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
|
||||
rwds_oe = "__________________________________________________________________________________"
|
||||
clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_____"
|
||||
cs_n = "----______________________________________________________________________________----"
|
||||
dq_oe = "______------------____________________________________________________________________"
|
||||
dq_o = "000000a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
|
||||
dq_i = "00000000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
|
||||
rwds_oe = "______________________________________________________________________________________"
|
||||
rwds_i = "______________________________________________________________--__--__--__--__________"
|
||||
yield
|
||||
for i in range(len(clk)):
|
||||
yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
|
||||
yield dut.pads.rwds.i.eq(c2bool(rwds_i[i]))
|
||||
self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
|
||||
self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
|
||||
self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
|
||||
|
|
@ -224,18 +232,19 @@ class TestHyperBus(unittest.TestCase):
|
|||
def fpga_gen(dut):
|
||||
dat = yield from dut.bus.read(0x1234)
|
||||
self.assertEqual(dat, 0xdeadbeef)
|
||||
dat = yield from dut.bus.read(0x1235)
|
||||
self.assertEqual(dat, 0xcafefade)
|
||||
|
||||
def hyperram_gen(dut):
|
||||
clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
|
||||
cs_n = "--________________________________________________________________________________________"
|
||||
dq_oe = "__------------____________________________________________________________________________"
|
||||
dq_o = "00a000048d00000000000000000000000000000000000000000000000000000000000000000000000000000000"
|
||||
dq_i = "000000000000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
|
||||
rwds_oe = "__________________________________________________________________________________________"
|
||||
clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_____"
|
||||
cs_n = "----______________________________________________________________________________________----"
|
||||
dq_oe = "______------------____________________________________________________________________________"
|
||||
dq_o = "000000a000048d00000000000000000000000000000000000000000000000000000000000000000000000000000000"
|
||||
dq_i = "0000000000000000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
|
||||
rwds_oe = "______________________________________________________________________________________________"
|
||||
rwds_i = "______________________________________________________________________--__--__--__--__________"
|
||||
yield
|
||||
for i in range(len(clk)):
|
||||
yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
|
||||
yield dut.pads.rwds.i.eq(c2bool(rwds_i[i]))
|
||||
self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
|
||||
self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
|
||||
self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
|
||||
|
|
@ -251,18 +260,19 @@ class TestHyperBus(unittest.TestCase):
|
|||
def fpga_gen(dut):
|
||||
dat = yield from dut.bus.read(0x1234)
|
||||
self.assertEqual(dat, 0xdeadbeef)
|
||||
dat = yield from dut.bus.read(0x1235)
|
||||
self.assertEqual(dat, 0xcafefade)
|
||||
|
||||
def hyperram_gen(dut):
|
||||
clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
|
||||
cs_n = "--____________________________________________________________"
|
||||
dq_oe = "__------------________________________________________________"
|
||||
dq_o = "00a000048d0000000000000000000000000000000000000000000000000000"
|
||||
dq_i = "00000000000000000000000000000000000000deadbeefcafefade00000000"
|
||||
rwds_oe = "______________________________________________________________"
|
||||
clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__-______"
|
||||
cs_n = "----________________________________________________________------"
|
||||
dq_oe = "______------------________________________________________________"
|
||||
dq_o = "000000a000048d0000000000000000000000000000000000000000000000000000"
|
||||
dq_i = "0000000000000000000000000000000000000000deadbeefcafefade0000000000"
|
||||
rwds_oe = "__________________________________________________________________"
|
||||
rwds_i = "________________________________________--__--__--__--____________"
|
||||
yield
|
||||
for i in range(len(clk)):
|
||||
yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
|
||||
yield dut.pads.rwds.i.eq(c2bool(rwds_i[i]))
|
||||
self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
|
||||
self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
|
||||
self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
|
||||
|
|
@ -276,22 +286,23 @@ class TestHyperBus(unittest.TestCase):
|
|||
|
||||
def test_hyperram_reg_write(self):
|
||||
def fpga_gen(dut):
|
||||
yield dut.reg_addr.eq(2)
|
||||
yield dut.reg_write_data.eq(0x1234)
|
||||
yield dut.core.reg.adr.eq(2)
|
||||
yield dut.core.reg.dat_w.eq(0x1234)
|
||||
yield
|
||||
yield dut.reg_write.eq(1)
|
||||
yield
|
||||
yield dut.reg_write.eq(0)
|
||||
for i in range(128):
|
||||
yield dut.core.reg.stb.eq(1)
|
||||
yield dut.core.reg.we.eq(1)
|
||||
while (yield dut.core.reg.ack) == 0:
|
||||
yield
|
||||
yield dut.core.reg.stb.eq(0)
|
||||
|
||||
def hyperram_gen(dut):
|
||||
clk = "_____--__--__--__--___________"
|
||||
cs_n = "----________________----------"
|
||||
dq_oe = "____----------------__________"
|
||||
dq_o = "000060000100000012340000000000"
|
||||
rwds_oe = "______________________________"
|
||||
rwds_o = "______________________________"
|
||||
clk = "___________--__--__--__--___________"
|
||||
cs_n = "--------__________________----------"
|
||||
dq_oe = "__________----------------__________"
|
||||
dq_o = "000000000060000100000012340000000000"
|
||||
rwds_oe = "____________________________________"
|
||||
rwds_o = "____________________________________"
|
||||
yield
|
||||
for i in range(len(clk)):
|
||||
self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
|
||||
self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
|
||||
|
|
@ -303,4 +314,4 @@ class TestHyperBus(unittest.TestCase):
|
|||
yield
|
||||
|
||||
dut = HyperRAM(HyperRamPads(), with_csr=False)
|
||||
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
|
||||
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")#
|
||||
Loading…
Reference in New Issue