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build/add_period_constraint: Simplify by using new integrated cases in generic add_period_constraint.
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53a0bc92e4
commit
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9 changed files with 0 additions and 28 deletions
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@ -45,9 +45,6 @@ class AlteraPlatform(GenericPlatform):
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return self.toolchain.build(self, *args, **kwargs)
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def add_period_constraint(self, clk, period):
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if clk is None: return
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if hasattr(clk, "p"):
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clk = clk.p
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self.toolchain.add_period_constraint(self, clk, period, keep=False)
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def add_false_path_constraint(self, from_, to):
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@ -204,12 +204,3 @@ class TangDinastyToolchain(GenericToolchain):
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(architecture, family, package) = devices[device]
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return (architecture, family, package)
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def add_period_constraint(self, platform, clk, period):
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clk.attr.add("keep")
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period = math.floor(period*1e3)/1e3 # round to lowest picosecond
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if clk in self.clocks:
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if period != self.clocks[clk]:
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raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
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.format(self.clocks[clk], period))
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self.clocks[clk] = period
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@ -36,5 +36,4 @@ class AnlogicPlatform(GenericPlatform):
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return self.toolchain.build(self, *args, **kwargs)
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def add_period_constraint(self, clk, period):
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if clk is None: return
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self.toolchain.add_period_constraint(self, clk, period)
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@ -63,9 +63,6 @@ class EfinixPlatform(GenericPlatform):
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return self.toolchain.build(self, *args, **kwargs)
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def add_period_constraint(self, clk, period):
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if clk is None: return
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if hasattr(clk, "p"):
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clk = clk.p
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self.toolchain.add_period_constraint(self, clk, period)
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def add_false_path_constraint(self, from_, to):
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@ -43,5 +43,4 @@ class GowinPlatform(GenericPlatform):
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return self.toolchain.build(self, *args, **kwargs)
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def add_period_constraint(self, clk, period):
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if clk is None: return
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self.toolchain.add_period_constraint(self, clk, period)
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@ -48,9 +48,6 @@ class LatticePlatform(GenericPlatform):
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return self.toolchain.build(self, *args, **kwargs)
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def add_period_constraint(self, clk, period):
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if clk is None: return
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if hasattr(clk, "p"):
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clk = clk.p
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self.toolchain.add_period_constraint(self, clk, period)
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def add_false_path_constraint(self, from_, to):
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@ -34,10 +34,6 @@ class MicrosemiPlatform(GenericPlatform):
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return self.toolchain.build(self, *args, **kwargs)
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def add_period_constraint(self, clk, period):
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if clk is None: return
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clk.attr.add("keep")
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if hasattr(clk, "p"):
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clk = clk.p
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self.toolchain.add_period_constraint(self, clk, period)
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def add_false_path_constraint(self, from_, to):
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@ -36,7 +36,6 @@ class OSFPGAPlatform(GenericPlatform):
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return self.toolchain.build(self, *args, **kwargs)
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def add_period_constraint(self, clk, period):
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if clk is None: return
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self.toolchain.add_period_constraint(self, clk, period)
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def add_false_path_constraint(self, from_, to):
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@ -85,9 +85,6 @@ class XilinxPlatform(GenericPlatform):
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return self.toolchain.build(self, *args, **kwargs)
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def add_period_constraint(self, clk, period, keep=True):
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if clk is None: return
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if hasattr(clk, "p"):
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clk = clk.p
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self.toolchain.add_period_constraint(self, clk, period, keep=keep)
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def add_false_path_constraint(self, from_, to):
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