Initial version
This commit is contained in:
Sebastien Bourdeauducq
commit
fb5130fc1f
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@ -0,0 +1,18 @@
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from migen.fhdl.structure import *
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class CRG:
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def get_clock_domains(self):
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r = dict()
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for k, v in self.__dict__.items():
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if isinstance(v, ClockDomain):
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r[v.name] = v
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return r
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def get_fragment(self):
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return Fragment()
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class SimpleCRG(CRG):
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def __init__(self, platform, clk_name, rst_name):
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self.cd = ClockDomain("sys")
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platform.request(clk_name, None, self.cd.clk)
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platform.request(rst_name, None, self.cd.rst)
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@ -0,0 +1,209 @@
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from copy import copy
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from migen.fhdl.structure import *
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from migen.corelogic.record import Record
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from migen.fhdl import verilog
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class ConstraintError(Exception):
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pass
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class Pins:
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def __init__(self, *identifiers):
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self.identifiers = identifiers
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class IOStandard:
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def __init__(self, name):
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self.name = name
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class Drive:
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def __init__(self, strength):
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self.strength = strength
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class Misc:
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def __init__(self, misc):
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self.misc = misc
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class Subsignal:
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def __init__(self, name, *constraints):
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self.name = name
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self.constraints = list(constraints)
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def _lookup(description, name, number):
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for resource in description:
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if resource[0] == name and (number is None or resource[1] == number):
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return resource
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return ConstraintError("Resource not found")
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def _resource_type(resource):
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t = None
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for element in resource[2:]:
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if isinstance(element, Pins):
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assert(t is None)
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t = len(element.identifiers)
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elif isinstance(element, Subsignal):
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if t is None:
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t = []
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assert(isinstance(t, list))
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n_bits = None
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for c in element.constraints:
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if isinstance(c, Pins):
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assert(n_bits is None)
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n_bits = len(c.identifiers)
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t.append((element.name, n_bits))
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return t
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def _match(description, requests):
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available = list(description)
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matched = []
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# 1. Match requests for a specific number
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for request in requests:
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if request[1] is not None:
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resource = _lookup(available, request[0], request[1])
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available.remove(resource)
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matched.append((resource, request[2]))
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# 2. Match requests for no specific number
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for request in requests:
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if request[1] is None:
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resource = _lookup(available, request[0], request[1])
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available.remove(resource)
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matched.append((resource, request[2]))
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return matched
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def _separate_pins(constraints):
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pins = None
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others = []
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for c in constraints:
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if isinstance(c, Pins):
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assert(pins is None)
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pins = c.identifiers
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else:
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others.append(c)
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return pins, others
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class ConstraintManager:
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def __init__(self, description):
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self.description = description
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self.requests = []
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self.platform_commands = []
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def request(self, name, number=None, obj=None):
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r = _lookup(self.description, name, number)
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t = _resource_type(r)
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# If obj is None, then create it.
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# If it already exists, do some sanity checking.
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if obj is None:
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if isinstance(t, int):
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obj = Signal(t, name_override=r[0])
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else:
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obj = Record(t)
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else:
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if isinstance(t, int):
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assert(isinstance(obj, Signal) and obj.nbits == t)
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else:
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for e in t:
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sig = getattr(obj, e[0])
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assert(isinstance(sig, Signal) and sig.nbits == e[1])
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# Register the request
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self.requests.append((name, number, obj))
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return obj
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def add_platform_command(self, command, **signals):
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self.platform_commands.append((command, signals))
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def get_io_signals(self):
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s = set()
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for req in self.requests:
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obj = req[2]
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if isinstance(obj, Signal):
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s.add(obj)
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else:
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for k in obj.__dict__:
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p = getattr(obj, k)
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if isinstance(p, Signal):
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s.add(p)
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return s
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def get_sig_constraints(self):
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r = []
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matched = _match(self.description, self.requests)
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for resource, obj in matched:
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name = resource[0]
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number = resource[1]
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has_subsignals = False
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top_constraints = []
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for element in resource[2:]:
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if isinstance(element, Subsignal):
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has_subsignals = True
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else:
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top_constraints.append(element)
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if has_subsignals:
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for element in resource[2:]:
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if isinstance(element, Subsignal):
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sig = getattr(obj, element.name)
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pins, others = _separate_pins(top_constraints + element.constraints)
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r.append((sig, pins, others, (name, number, element.name)))
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else:
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pins, others = _separate_pins(top_constraints)
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r.append((obj, pins, others, (name, number, None)))
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return r
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def get_platform_commands(self):
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return self.platform_commands
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def save(self):
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return copy(self.requests), copy(self.platform_commands)
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def restore(self, backup):
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self.request, self.platform_commands = backup
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class GenericPlatform:
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def __init__(self, device, io, default_crg_factory=None):
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self.device = device
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self.constraint_manager = ConstraintManager(io)
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self.default_crg_factory = default_crg_factory
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def request(self, *args, **kwargs):
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return self.constraint_manager.request(*args, **kwargs)
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def add_platform_command(self, *args, **kwargs):
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return self.constraint_manager.add_platform_command(*args, **kwargs)
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def get_verilog(self, fragment, clock_domains=None):
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# We may create a temporary clock/reset generator that would request pins.
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# Save the constraint manager state so that such pin requests disappear
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# at the end of this function.
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backup = self.constraint_manager.save()
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try:
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# if none exists, create a default clock domain and drive it
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if clock_domains is None:
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if self.default_crg_factory is None:
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raise NotImplementedError("No clock/reset generator defined by either platform or user")
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crg = self.default_crg_factory(self)
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frag = fragment + crg.get_fragment()
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clock_domains = crg.get_clock_domains()
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else:
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frag = fragment
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# generate Verilog
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src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(),
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clock_domains=clock_domains, return_ns=True)
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# resolve signal names in constraints
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sc = self.constraint_manager.get_sig_constraints()
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named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]
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# resolve signal names in platform commands
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pc = self.constraint_manager.get_platform_commands()
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named_pc = []
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for template, args in pc:
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name_dict = dict((k, vns.get_name(sig)) for k, sig in args.items())
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named_pc.append(template.format(**name_dict))
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finally:
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self.constraint_manager.restore(backup)
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return src, named_sc, named_pc
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def build(self, fragment, clock_domains=None):
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raise NotImplementedError("GenericPlatform.build must be overloaded")
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@ -0,0 +1,131 @@
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from mibuild.generic_platform import *
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from mibuild.xilinx_ise import XilinxISEPlatform, CRG_DS
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_io = [
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("user_led", 0, Pins("Y3")),
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("user_led", 1, Pins("Y1")),
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("user_led", 2, Pins("W2")),
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("user_led", 3, Pins("W1")),
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("user_led", 4, Pins("V3")),
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("user_led", 5, Pins("V1")),
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("user_led", 6, Pins("U2")),
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("user_led", 7, Pins("U1")),
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("clk100", 0,
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Subsignal("p", Pins("B14"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")),
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Subsignal("n", Pins("A14"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"))
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),
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("gpio", 0, Pins("R8")),
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("gpmc", 0,
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Subsignal("clk", Pins("R26")),
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Subsignal("a", Pins("N17", "N18", "L23", "L24", "N19", "N20", "N21", "N22", "P17", "P19")),
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Subsignal("d", Pins("N23", "N24", "R18", "R19", "P21", "P22", "R20", "R21", "P24", "P26", "R23", "R24", "T22", "T23", "U23", "R25")),
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Subsignal("we_n", Pins("W26")),
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Subsignal("oe_n", Pins("AA25")),
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Subsignal("ale_n", Pins("AA26")),
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IOStandard("LVCMOS33")),
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# Warning: CS are numbered 1-7 on ARM side and 0-6 on FPGA side.
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# Numbers here are given on the FPGA side.
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("gpmc_ce_n", 0, Pins("V23"), IOStandard("LVCMOS33")), # nCS0
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("gpmc_ce_n", 1, Pins("U25"), IOStandard("LVCMOS33")), # nCS1
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("gpmc_ce_n", 2, Pins("W25"), IOStandard("LVCMOS33")), # nCS6
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("gpmc_dmareq_n", 0, Pins("T24"), IOStandard("LVCMOS33")), # nCS2
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("gpmc_dmareq_n", 1, Pins("T26"), IOStandard("LVCMOS33")), # nCS3
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("gpmc_dmareq_n", 2, Pins("V24"), IOStandard("LVCMOS33")), # nCS4
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("gpmc_dmareq_n", 3, Pins("V26"), IOStandard("LVCMOS33")), # nCS5
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# FMC150
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("fmc150_ctrl", 0,
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Subsignal("spi_sclk", Pins("AE5")),
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Subsignal("spi_data", Pins("AF5")),
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Subsignal("adc_sdo", Pins("U13")),
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Subsignal("adc_en_n", Pins("AA15")),
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Subsignal("adc_reset", Pins("V13")),
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Subsignal("cdce_sdo", Pins("AA8")),
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Subsignal("cdce_en_n", Pins("Y9")),
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Subsignal("cdce_reset_n", Pins("AB7")),
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Subsignal("cdce_pd_n", Pins("AC6")),
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Subsignal("cdce_pll_status", Pins("W7")),
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Subsignal("cdce_ref_en", Pins("W8")),
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Subsignal("dac_sdo", Pins("W9")),
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Subsignal("dac_en_n", Pins("W10")),
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Subsignal("mon_sdo", Pins("AC5")),
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Subsignal("mon_en_n", Pins("AD6")),
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Subsignal("mon_reset_n", Pins("AF6")),
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Subsignal("mon_int_n", Pins("AD5")),
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Subsignal("pg_c2m", Pins("AA23"), IOStandard("LVCMOS33"))
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),
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("ti_dac", 0, # DAC3283
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Subsignal("dat_p", Pins("AA10", "AA9", "V11", "Y11", "W14", "Y12", "AD14", "AE13"), IOStandard("LVDS_25")),
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Subsignal("dat_n", Pins("AB11", "AB9", "V10", "AA11", "Y13", "AA12", "AF14", "AF13"), IOStandard("LVDS_25")),
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Subsignal("frame_p", Pins("AB13"), IOStandard("LVDS_25")),
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Subsignal("frame_n", Pins("AA13"), IOStandard("LVDS_25")),
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Subsignal("txenable", Pins("AB15"), IOStandard("LVCMOS25"))
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),
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("ti_adc", 0, # ADS62P49
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Subsignal("dat_a_p", Pins("AB14", "Y21", "W20", "AB22", "V18", "W17", "AA21")),
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Subsignal("dat_a_n", Pins("AC14", "AA22", "Y20", "AC22", "W19", "W18", "AB21")),
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Subsignal("dat_b_p", Pins("Y17", "U15", "AA19", "W16", "AA18", "Y15", "V14")),
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Subsignal("dat_b_n", Pins("AA17", "V16", "AB19", "Y16", "AB17", "AA16", "V15")),
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IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
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),
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("fmc150_clocks", 0,
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Subsignal("dac_clk_p", Pins("V12"), IOStandard("LVDS_25")),
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Subsignal("dac_clk_n", Pins("W12"), IOStandard("LVDS_25")),
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Subsignal("adc_clk_p", Pins("AE15"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")),
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Subsignal("adc_clk_n", Pins("AF15"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")),
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Subsignal("clk_to_fpga", Pins("W24"), IOStandard("LVCMOS25"))
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),
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("fmc150_ext_trigger", 0, Pins("U26")),
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# Vermeer radar testbed
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# TX path
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("pe43602", 0,
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Subsignal("d", Pins("H8")),
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Subsignal("clk", Pins("B3")),
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Subsignal("le", Pins("F7")),
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IOStandard("LVCMOS33")
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),
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("rfmd2081", 0,
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Subsignal("enx", Pins("E5")),
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Subsignal("sclk", Pins("G6")),
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Subsignal("sdata", Pins("F5")),
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Subsignal("sdatao", Pins("E6")),
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IOStandard("LVCMOS33")
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),
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# RX path
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("lmh6521", 0,
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Subsignal("scsb", Pins("C5")),
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Subsignal("sclk", Pins("G10")),
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Subsignal("sdi", Pins("D5")),
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Subsignal("sdo", Pins("F9")),
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IOStandard("LVCMOS33")
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),
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("lmh6521", 1,
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Subsignal("scsb", Pins("E10")),
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Subsignal("sclk", Pins("A4")),
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Subsignal("sdi", Pins("B4")),
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Subsignal("sdo", Pins("H10")),
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IOStandard("LVCMOS33")
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),
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("rffc5071", 0,
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Subsignal("enx", Pins("A2")),
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Subsignal("sclk", Pins("G9")),
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Subsignal("sdata", Pins("H9")),
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Subsignal("sdatao", Pins("A3")),
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IOStandard("LVCMOS33")
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)
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]
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class Platform(XilinxISEPlatform):
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def __init__(self):
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XilinxISEPlatform.__init__(self, "xc6slx150t-fgg676-3", _io,
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lambda p: CRG_DS(p, "clk100", "gpio", 10.0))
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|
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@ -0,0 +1,12 @@
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import os
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def mkdir_noerror(d):
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try:
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os.mkdir(d)
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except OSError:
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pass
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def write_to_file(filename, contents):
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f = open(filename, "w")
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f.write(contents)
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f.close()
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@ -0,0 +1,122 @@
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import os, struct, subprocess
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from decimal import Decimal
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from migen.fhdl.structure import *
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from mibuild.generic_platform import *
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from mibuild.crg import CRG, SimpleCRG
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from mibuild import tools
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def _add_period_constraint(platform, clk, period):
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platform.add_platform_command("""NET "{clk}" TNM_NET = "GRPclk";
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TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk)
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class CRG_SE(SimpleCRG):
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def __init__(self, platform, clk_name, rst_name, period):
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SimpleCRG.__init__(self, platform, clk_name, rst_name)
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_add_period_constraint(platform, self.cd.clk, period)
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class CRG_DS(CRG):
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def __init__(self, platform, clk_name, rst_name, period):
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self.cd = ClockDomain("sys")
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self._clk = platform.request(clk_name)
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platform.request(rst_name, None, self.cd.rst)
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_add_period_constraint(platform, self._clk.p, period)
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def get_fragment(self):
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ibufg = Instance("IBUFGDS",
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Instance.Input("I", self._clk.p),
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Instance.Input("IB", self._clk.n),
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Instance.Output("O", self.cd.clk)
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)
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return Fragment(instances=[ibufg])
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def _format_constraint(c):
|
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if isinstance(c, Pins):
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return "LOC=" + c.identifiers[0]
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elif isinstance(c, IOStandard):
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return "IOSTANDARD=" + c.name
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elif isinstance(c, Drive):
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return "DRIVE=" + str(c.strength)
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elif isinstance(c, Misc):
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return c.misc
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def _format_ucf(signame, pin, others, resname):
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fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)]
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fmt_r = resname[0] + ":" + str(resname[1])
|
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if resname[2] is not None:
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fmt_r += "." + resname[2]
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return "NET \"" + signame + "\" " + " | ".join(fmt_c) + "; # " + fmt_r + "\n"
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||||
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def _build_ucf(named_sc, named_pc):
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r = ""
|
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for sig, pins, others, resname in named_sc:
|
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if len(pins) > 1:
|
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for i, p in enumerate(pins):
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r += _format_ucf(sig + "(" + str(i) + ")", p, others, resname)
|
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else:
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r += _format_ucf(sig, pins[0], others, resname)
|
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if named_pc:
|
||||
r += "\n" + "\n\n".join(named_pc)
|
||||
return r
|
||||
|
||||
def _build(device, sources, named_sc, named_pc, build_name, xilinx_install_path):
|
||||
tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
|
||||
|
||||
prj_contents = ""
|
||||
for s in sources:
|
||||
prj_contents += s["type"] + " work " + s["path"] + "\n"
|
||||
tools.write_to_file(build_name + ".prj", prj_contents)
|
||||
|
||||
xst_contents = """run
|
||||
-ifn %s.prj
|
||||
-top top
|
||||
-ifmt MIXED
|
||||
-opt_mode SPEED
|
||||
-reduce_control_sets auto
|
||||
-ofn %s.ngc
|
||||
-p %s""" % (build_name, build_name, device)
|
||||
tools.write_to_file(build_name + ".xst", xst_contents)
|
||||
|
||||
def is_valid_version(v):
|
||||
try:
|
||||
Decimal(v)
|
||||
return os.path.isdir(os.path.join(xilinx_install_path, v))
|
||||
except:
|
||||
return False
|
||||
vers = [ver for ver in os.listdir(xilinx_install_path) if is_valid_version(ver)]
|
||||
tools_version = max(vers)
|
||||
bits = struct.calcsize("P")*8
|
||||
xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (xilinx_install_path, tools_version, bits)
|
||||
|
||||
build_script_contents = """# Autogenerated by mibuild
|
||||
|
||||
set -e
|
||||
|
||||
source {xilinx_settings_file}
|
||||
xst -ifn {build_name}.xst
|
||||
ngdbuild -uc {build_name}.ucf {build_name}.ngc
|
||||
map -ol high -w {build_name}.ngd
|
||||
par -ol high -w {build_name}.ncd {build_name}-routed.ncd
|
||||
bitgen -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit
|
||||
""".format(build_name=build_name, xilinx_settings_file=xilinx_settings_file)
|
||||
build_script_file = "build_" + build_name + ".sh"
|
||||
tools.write_to_file(build_script_file, build_script_contents)
|
||||
|
||||
r = subprocess.call(["bash", build_script_file])
|
||||
if r != 0:
|
||||
raise OSError("Subprocess failed")
|
||||
|
||||
class XilinxISEPlatform(GenericPlatform):
|
||||
def build(self, fragment, clock_domains=None, build_dir="build", build_name="top",
|
||||
xilinx_install_path="/opt/Xilinx"):
|
||||
tools.mkdir_noerror(build_dir)
|
||||
os.chdir(build_dir)
|
||||
|
||||
v_src, named_sc, named_pc = self.get_verilog(fragment, clock_domains)
|
||||
v_file = build_name + ".v"
|
||||
tools.write_to_file(v_file, v_src)
|
||||
sources = [{"type": "verilog", "path": v_file}]
|
||||
_build(self.device, sources, named_sc, named_pc, build_name, xilinx_install_path)
|
||||
|
||||
os.chdir("..")
|
||||
Loading…
Reference in New Issue