uart: remove litescope dependency for UARTWishboneBridge and remove frontend

misoclib/com/liteeth/example_designs/targets/base.py

@@ -7,7 +7,7 @@ from misoclib.tools.litescope.common import *
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
+from misoclib.com.uart.wishbone import UARTWishboneBridge
 
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII

misoclib/com/litepcie/example_designs/targets/dma.py

@@ -7,7 +7,7 @@ from migen.genlib.misc import timeline
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
 
-from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
+from misoclib.com.uart.wishbone import UARTWishboneBridge
 
 from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY
 from misoclib.com.litepcie.core import Endpoint

misoclib/com/liteusb/frontend/wishbone.py

@@ -1,9 +1,9 @@
 from migen.fhdl.std import *
 
 from misoclib.com.liteusb.common import *
-from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
+from misoclib.tools.wishbone import WishboneStreamingBridge
 
-class LiteUSBWishboneBridge(LiteScopeWishboneBridge):
+class LiteUSBWishboneBridge(WishboneStreamingBridge):
     def __init__(self, port, clk_freq):
-        LiteScopeWishboneBridge.__init__(self, port, clk_freq)
+        WishboneStreamingBridge.__init__(self, port, clk_freq)
         self.comb += port.sink.dst.eq(port.tag)

misoclib/com/uart/wishbone.py

@@ -1,9 +1,9 @@
 from migen.fhdl.std import *
 
-from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
+from misoclib.tools.wishbone import WishboneStreamingBridge
 from misoclib.com.uart.phy.serial import UARTPHYSerial
 
-class UARTWishboneBridge(LiteScopeWishboneBridge):
+class UARTWishboneBridge(WishboneStreamingBridge):
     def __init__(self, pads, clk_freq, baudrate=115200):
         self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
-        LiteScopeWishboneBridge.__init__(self, self.phy, clk_freq)
+        WishboneStreamingBridge.__init__(self, self.phy, clk_freq)

misoclib/mem/litesata/example_designs/targets/bist.py

@@ -9,7 +9,7 @@ from misoclib.tools.litescope.common import *
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
+from misoclib.com.uart.wishbone import UARTWishboneBridge
 
 from misoclib.mem.litesata.common import *
 from misoclib.mem.litesata.phy import LiteSATAPHY

misoclib/tools/litescope/example_designs/targets/simple.py

@@ -7,7 +7,7 @@ from misoclib.tools.litescope.core.port import LiteScopeTerm
 from misoclib.tools.litescope.frontend.io import LiteScopeIO
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 
-from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
+from misoclib.com.uart.wishbone import UARTWishboneBridge
 
 class LiteScopeSoC(SoC, AutoCSR):
     csr_map = {

misoclib/tools/wishbone.py

@@ -1,12 +1,12 @@
-from misoclib.tools.litescope.common import *
+from migen.fhdl.std import *
 from migen.bus import wishbone
-from migen.genlib.misc import chooser
+from migen.genlib.misc import chooser, Counter, Timeout
 from migen.genlib.record import Record
+from migen.genlib.fsm import FSM, NextState
 from migen.flow.actor import Sink, Source
 
-from misoclib.com.uart.phy.serial import UARTPHYSerial
 
-class LiteScopeWishboneBridge(Module):
+class WishboneStreamingBridge(Module):
     cmds = {
         "write": 0x01,
         "read": 0x02