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uart: remove litescope dependency for UARTWishboneBridge and remove frontend

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This commit is contained in:
Florent Kermarrec 2015-05-09 15:48:54 +02:00
parent 1fd189512f
commit fb5397aa82
8 changed files with 14 additions and 14 deletions
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2
misoclib/com/liteeth/example_designs/targets/base.py
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@ -7,7 +7,7 @@ from misoclib.tools.litescope.common import *
from misoclib.tools.litescope.frontend.la import LiteScopeLA
from misoclib.tools.litescope.core.port import LiteScopeTerm
from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
from misoclib.com.uart.wishbone import UARTWishboneBridge
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII

2
misoclib/com/litepcie/example_designs/targets/dma.py
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@ -7,7 +7,7 @@ from migen.genlib.misc import timeline
from misoclib.soc import SoC
from misoclib.tools.litescope.common import *
from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
from misoclib.com.uart.wishbone import UARTWishboneBridge
from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY
from misoclib.com.litepcie.core import Endpoint

6
misoclib/com/liteusb/frontend/wishbone.py
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@ -1,9 +1,9 @@
from migen.fhdl.std import *
from misoclib.com.liteusb.common import *
from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
from misoclib.tools.wishbone import WishboneStreamingBridge
class LiteUSBWishboneBridge(LiteScopeWishboneBridge):
class LiteUSBWishboneBridge(WishboneStreamingBridge):
def __init__(self, port, clk_freq):
LiteScopeWishboneBridge.__init__(self, port, clk_freq)
WishboneStreamingBridge.__init__(self, port, clk_freq)
self.comb += port.sink.dst.eq(port.tag)

0
misoclib/com/uart/frontend/__init__.py
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6
misoclib/com/uart/frontend/wishbone.py → misoclib/com/uart/wishbone.py
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@ -1,9 +1,9 @@
from migen.fhdl.std import *
from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
from misoclib.tools.wishbone import WishboneStreamingBridge
from misoclib.com.uart.phy.serial import UARTPHYSerial
class UARTWishboneBridge(LiteScopeWishboneBridge):
class UARTWishboneBridge(WishboneStreamingBridge):
def __init__(self, pads, clk_freq, baudrate=115200):
self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
LiteScopeWishboneBridge.__init__(self, self.phy, clk_freq)
WishboneStreamingBridge.__init__(self, self.phy, clk_freq)

2
misoclib/mem/litesata/example_designs/targets/bist.py
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@ -9,7 +9,7 @@ from misoclib.tools.litescope.common import *
from misoclib.tools.litescope.frontend.la import LiteScopeLA
from misoclib.tools.litescope.core.port import LiteScopeTerm
from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
from misoclib.com.uart.wishbone import UARTWishboneBridge
from misoclib.mem.litesata.common import *
from misoclib.mem.litesata.phy import LiteSATAPHY

2
misoclib/tools/litescope/example_designs/targets/simple.py
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@ -7,7 +7,7 @@ from misoclib.tools.litescope.core.port import LiteScopeTerm
from misoclib.tools.litescope.frontend.io import LiteScopeIO
from misoclib.tools.litescope.frontend.la import LiteScopeLA
from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
from misoclib.com.uart.wishbone import UARTWishboneBridge
class LiteScopeSoC(SoC, AutoCSR):
csr_map = {

8
misoclib/tools/litescope/frontend/wishbone.py → misoclib/tools/wishbone.py
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@ -1,12 +1,12 @@
from misoclib.tools.litescope.common import *
from migen.fhdl.std import *
from migen.bus import wishbone
from migen.genlib.misc import chooser
from migen.genlib.misc import chooser, Counter, Timeout
from migen.genlib.record import Record
from migen.genlib.fsm import FSM, NextState
from migen.flow.actor import Sink, Source
from misoclib.com.uart.phy.serial import UARTPHYSerial
class LiteScopeWishboneBridge(Module):
class WishboneStreamingBridge(Module):
cmds = {
"write": 0x01,
"read": 0x02