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soc_core: remove static 16MB csr region allocation (use csr_address_width to allocate the correct size)

This commit is contained in:
Florent Kermarrec 2019-12-12 12:41:25 +01:00
parent b1a1e5e227
commit fb6b0786b6
1 changed files with 1 additions and 2 deletions
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3
litex/soc/integration/soc_core.py
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@ -138,7 +138,6 @@ class SoCCore(Module):
self.integrated_main_ram_size = integrated_main_ram_size self.integrated_main_ram_size = integrated_main_ram_size
assert csr_data_width in [8, 32, 64] assert csr_data_width in [8, 32, 64]
assert 2**(csr_address_width + 2) <= 0x1000000
self.csr_data_width = csr_data_width self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width self.csr_address_width = csr_address_width
@ -266,7 +265,7 @@ class SoCCore(Module):
address_width = csr_address_width, address_width = csr_address_width,
data_width = csr_data_width)) data_width = csr_data_width))
self.add_csr_master(self.wishbone2csr.csr) self.add_csr_master(self.wishbone2csr.csr)
self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000) self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 2**(csr_address_width + 2))
# Methods -------------------------------------------------------------------------------------- # Methods --------------------------------------------------------------------------------------