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dvisampler: report the word error rate
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3 changed files with 72 additions and 1 deletions
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@ -6,6 +6,7 @@ from milkymist.dvisampler.edid import EDID
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from milkymist.dvisampler.clocking import Clocking
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from milkymist.dvisampler.datacapture import DataCapture
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from milkymist.dvisampler.charsync import CharSync
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from milkymist.dvisampler.wer import WER
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from milkymist.dvisampler.decoding import Decoding
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from milkymist.dvisampler.chansync import ChanSync
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from milkymist.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
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@ -36,6 +37,10 @@ class DVISampler(Module, AutoCSR):
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setattr(self.submodules, name + "_charsync", charsync)
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self.comb += charsync.raw_data.eq(cap.d)
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wer = WER()
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setattr(self.submodules, name + "_wer", wer)
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self.comb += wer.data.eq(charsync.data)
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decoding = Decoding()
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setattr(self.submodules, name + "_decod", decoding)
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self.comb += [
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60
milkymist/dvisampler/wer.py
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60
milkymist/dvisampler/wer.py
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@ -0,0 +1,60 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bank.description import *
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from migen.genlib.misc import optree
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from migen.genlib.cdc import PulseSynchronizer
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from milkymist.dvisampler.common import control_tokens
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class WER(Module, AutoCSR):
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def __init__(self, period_bits=24):
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self.data = Signal(10)
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self._r_update = CSR()
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self._r_value = CSRStatus(period_bits)
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###
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# pipeline stage 1
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# we ignore the 10th (inversion) bit, as it is independent of the transition minimization
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data_r = Signal(9)
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self.sync.pix += data_r.eq(self.data[:9])
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# pipeline stage 2
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transitions = Signal(8)
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self.comb += [transitions[i].eq(data_r[i] ^ data_r[i+1]) for i in range(8)]
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transition_count = Signal(max=9)
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self.sync.pix += transition_count.eq(optree("+", [transitions[i] for i in range(8)]))
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is_control = Signal()
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self.sync.pix += is_control.eq(optree("|", [data_r == ct for ct in control_tokens]))
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# pipeline stage 3
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is_error = Signal()
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self.sync.pix += is_error.eq((transition_count > 4) & ~is_control)
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# counter
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period_counter = Signal(period_bits)
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period_done = Signal()
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self.sync.pix += Cat(period_counter, period_done).eq(period_counter + 1)
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wer_counter = Signal(period_bits)
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wer_counter_r = Signal(period_bits)
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wer_counter_r_updated = Signal()
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self.sync.pix += [
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wer_counter_r_updated.eq(period_done),
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If(period_done,
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wer_counter_r.eq(wer_counter),
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wer_counter.eq(0)
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).Elif(is_error,
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wer_counter.eq(wer_counter + 1)
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)
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]
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# sync to system clock domain
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wer_counter_sys = Signal(period_bits)
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self.submodules.ps_counter = PulseSynchronizer("pix", "sys")
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self.comb += self.ps_counter.i.eq(wer_counter_r_updated)
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self.sync += If(self.ps_counter.o, wer_counter_sys.eq(wer_counter_r))
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# register interface
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self.sync += If(self._r_update.re, self._r_value.status.eq(wer_counter_sys))
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@ -65,7 +65,10 @@ static int dvisamplerX_d0, dvisamplerX_d1, dvisamplerX_d2;
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void dvisamplerX_print_status(void)
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{
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printf("dvisamplerX: ph:%4d %4d %4d // charsync:%d%d%d [%d %d %d] // chansync:%d // res:%dx%d\n",
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dvisamplerX_data0_wer_update_write(1);
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dvisamplerX_data1_wer_update_write(1);
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dvisamplerX_data2_wer_update_write(1);
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printf("dvisamplerX: ph:%4d %4d %4d // charsync:%d%d%d [%d %d %d] // WER:%3d %3d %3d // chansync:%d // res:%dx%d\n",
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dvisamplerX_d0, dvisamplerX_d1, dvisamplerX_d2,
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dvisamplerX_data0_charsync_char_synced_read(),
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dvisamplerX_data1_charsync_char_synced_read(),
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@ -73,6 +76,9 @@ void dvisamplerX_print_status(void)
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dvisamplerX_data0_charsync_ctl_pos_read(),
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dvisamplerX_data1_charsync_ctl_pos_read(),
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dvisamplerX_data2_charsync_ctl_pos_read(),
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dvisamplerX_data0_wer_value_read(),
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dvisamplerX_data1_wer_value_read(),
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dvisamplerX_data2_wer_value_read(),
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dvisamplerX_chansync_channels_synced_read(),
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dvisamplerX_resdetection_hres_read(),
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dvisamplerX_resdetection_vres_read());
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