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Merge pull request #1512 from antmicro/liblitedram_cleanup 

Liblitedram cleanup
This commit is contained in:
enjoy-digital 2023-01-26 18:50:51 +01:00 committed by GitHub
parent 155bf31e04 68877742b1
commit fb94cb0551
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GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 745 additions and 588 deletions
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99
litex/soc/software/bios/cmds/cmd_litedram.c
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@ -14,50 +14,11 @@
#include <liblitedram/sdram.h>
#include <liblitedram/sdram_spd.h>
#include <liblitedram/bist.h>
#include <liblitedram/accessors.h>
#include "../command.h"
#include "../helpers.h"
/**
* Command "sdram_init"
*
* Initialize SDRAM (Init + Calibration)
*
*/
#if defined(CSR_SDRAM_BASE)
define_command(sdram_init, sdram_init, "Initialize SDRAM (Init + Calibration)", LITEDRAM_CMDS);
#endif
/**
* Command "sdram_cal"
*
* Calibrate SDRAM
*
*/
#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
static void sdram_cal_handler(int nb_params, char **params)
{
sdram_software_control_on();
sdram_leveling();
sdram_software_control_off();
}
define_command(sdram_cal, sdram_cal_handler, "Calibrate SDRAM", LITEDRAM_CMDS);
#endif
/**
* Command "sdram_test"
*
* Test SDRAM
*
*/
#if defined(CSR_SDRAM_BASE)
static void sdram_test_handler(int nb_params, char **params)
{
memtest((unsigned int *)MAIN_RAM_BASE, MAIN_RAM_SIZE/32);
}
define_command(sdram_test, sdram_test_handler, "Test SDRAM", LITEDRAM_CMDS);
#endif
/**
* Command "sdram_bist"
*
@ -228,7 +189,44 @@ define_command(sdram_force_cmd_delay, sdram_force_cmd_delay_handler, "Force writ
#endif
#ifdef CSR_DDRPHY_WDLY_DQ_RST_ADDR
#if defined(CSR_SDRAM_BASE)
/**
* Command "sdram_init"
*
* Initialize SDRAM (Init + Calibration)
*
*/
define_command(sdram_init, sdram_init, "Initialize SDRAM (Init + Calibration)", LITEDRAM_CMDS);
/**
* Command "sdram_test"
*
* Test SDRAM
*
*/
static void sdram_test_handler(int nb_params, char **params)
{
memtest((unsigned int *)MAIN_RAM_BASE, MAIN_RAM_SIZE/32);
}
define_command(sdram_test, sdram_test_handler, "Test SDRAM", LITEDRAM_CMDS);
/**
* Command "sdram_cal"
*
* Calibrate SDRAM
*
*/
#if defined(CSR_DDRPHY_BASE)
static void sdram_cal_handler(int nb_params, char **params)
{
sdram_software_control_on();
sdram_leveling();
sdram_software_control_off();
}
define_command(sdram_cal, sdram_cal_handler, "Calibrate SDRAM", LITEDRAM_CMDS);
#endif
#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
/**
* Command "sdram_rst_dat_delay"
@ -236,7 +234,7 @@ define_command(sdram_force_cmd_delay, sdram_force_cmd_delay_handler, "Force writ
* Reset write leveling Dat delay
*
*/
#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
#if defined(CSR_DDRPHY_BASE)
static void sdram_rst_dat_delay_handler(int nb_params, char **params)
{
char *c;
@ -263,7 +261,7 @@ define_command(sdram_rst_dat_delay, sdram_rst_dat_delay_handler, "Reset write le
* Force write leveling Dat delay
*
*/
#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
#if defined(CSR_DDRPHY_BASE)
static void sdram_force_dat_delay_handler(int nb_params, char **params)
{
char *c;
@ -288,15 +286,18 @@ static void sdram_force_dat_delay_handler(int nb_params, char **params)
sdram_software_control_off();
}
define_command(sdram_force_dat_delay, sdram_force_dat_delay_handler, "Force write leveling Dat delay", LITEDRAM_CMDS);
#endif
#endif /* defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE) */
#endif /* SDRAM_PHY_WRITE_LEVELING_CAPABLE */
#if defined(SDRAM_PHY_BITSLIPS) && defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE)
/**
* Command "sdram_rst_bitslip"
*
* Reset write leveling Bitslip
*
*/
#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
#if defined(CSR_DDRPHY_BASE)
static void sdram_rst_bitslip_handler(int nb_params, char **params)
{
char *c;
@ -323,7 +324,7 @@ define_command(sdram_rst_bitslip, sdram_rst_bitslip_handler, "Reset write leveli
* Force write leveling Bitslip
*
*/
#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
#if defined(CSR_DDRPHY_BASE)
static void sdram_force_bitslip_handler(int nb_params, char **params)
{
char *c;
@ -350,7 +351,7 @@ static void sdram_force_bitslip_handler(int nb_params, char **params)
define_command(sdram_force_bitslip, sdram_force_bitslip_handler, "Force write leveling Bitslip", LITEDRAM_CMDS);
#endif
#endif
#endif /* defined(SDRAM_PHY_BITSLIPS) && defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE) */
/**
* Command "sdram_mr_write"
@ -358,7 +359,6 @@ define_command(sdram_force_bitslip, sdram_force_bitslip_handler, "Force write le
* Write SDRAM Mode Register
*
*/
#if defined(CSR_SDRAM_BASE)
static void sdram_mr_write_handler(int nb_params, char **params)
{
char *c;
@ -385,7 +385,8 @@ static void sdram_mr_write_handler(int nb_params, char **params)
sdram_software_control_off();
}
define_command(sdram_mr_write, sdram_mr_write_handler, "Write SDRAM Mode Register", LITEDRAM_CMDS);
#endif
#endif /* CSR_SDRAM_BASE */
/**
* Command "sdram_spd"

2
litex/soc/software/liblitedram/Makefile
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@ -1,7 +1,7 @@
include ../include/generated/variables.mak
include $(SOC_DIRECTORY)/software/common.mak
OBJECTS = sdram.o bist.o sdram_dbg.o sdram_spd.o utils.o
OBJECTS = sdram.o bist.o sdram_dbg.o sdram_spd.o utils.o accessors.o
all: liblitedram.a

193
litex/soc/software/liblitedram/accessors.c Normal file
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@ -0,0 +1,193 @@
#include <stdio.h>
#include <liblitedram/accessors.h>
#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
#if defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
int read_dq_delay[SDRAM_PHY_MODULES];
void read_inc_dq_delay(int module) {
/* Increment delay */
read_dq_delay[module] = (read_dq_delay[module] + 1) & (SDRAM_PHY_DELAYS - 1);
ddrphy_rdly_dq_inc_write(1);
}
void read_rst_dq_delay(int module) {
/* Reset delay */
read_dq_delay[module] = 0;
ddrphy_rdly_dq_rst_write(1);
}
#endif // defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
#if defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE)
int sdram_clock_delay;
void sdram_inc_clock_delay(void) {
sdram_clock_delay = (sdram_clock_delay + 1) & (SDRAM_PHY_DELAYS - 1);
ddrphy_cdly_inc_write(1);
cdelay(100);
}
void sdram_rst_clock_delay(void) {
sdram_clock_delay = 0;
ddrphy_cdly_rst_write(1);
cdelay(100);
}
int write_dq_delay[SDRAM_PHY_MODULES];
void write_inc_dq_delay(int module) {
/* Increment DQ delay */
write_dq_delay[module] = (write_dq_delay[module] + 1) & (SDRAM_PHY_DELAYS - 1);
ddrphy_wdly_dq_inc_write(1);
cdelay(100);
}
void write_rst_dq_delay(int module) {
#if defined(SDRAM_PHY_USDDRPHY) || defined(SDRAM_PHY_USPDDRPHY)
/* Reset DQ delay */
int dq_count = ddrphy_wdly_dqs_inc_count_read();
while (dq_count != SDRAM_PHY_DELAYS) {
ddrphy_wdly_dq_inc_write(1);
cdelay(100);
dq_count++;
}
#else
/* Reset DQ delay */
ddrphy_wdly_dq_rst_write(1);
cdelay(100);
#endif //defined(SDRAM_PHY_USDDRPHY) || defined(SDRAM_PHY_USPDDRPHY)
write_dq_delay[module] = 0;
}
void write_inc_dqs_delay(int module) {
/* Increment DQS delay */
ddrphy_wdly_dqs_inc_write(1);
cdelay(100);
}
void write_rst_dqs_delay(int module) {
#if defined(SDRAM_PHY_USDDRPHY) || defined(SDRAM_PHY_USPDDRPHY)
/* Reset DQS delay */
while (ddrphy_wdly_dqs_inc_count_read() != 0) {
ddrphy_wdly_dqs_inc_write(1);
cdelay(100);
}
#else
/* Reset DQS delay */
ddrphy_wdly_dqs_rst_write(1);
cdelay(100);
#endif //defined(SDRAM_PHY_USDDRPHY) || defined(SDRAM_PHY_USPDDRPHY)
}
void write_inc_delay(int module) {
/* Increment DQ/DQS delay */
write_inc_dq_delay(module);
write_inc_dqs_delay(module);
}
void write_rst_delay(int module) {
write_rst_dq_delay(module);
write_rst_dqs_delay(module);
}
#endif // defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE)
#if defined(SDRAM_PHY_BITSLIPS)
int read_dq_bitslip[SDRAM_PHY_MODULES];
void read_inc_dq_bitslip(int module) {
/* Increment bitslip */
read_dq_bitslip[module] = (read_dq_bitslip[module] + 1) & (SDRAM_PHY_BITSLIPS - 1);
ddrphy_rdly_dq_bitslip_write(1);
}
void read_rst_dq_bitslip(int module) {
/* Reset bitslip */
read_dq_bitslip[module] = 0;
ddrphy_rdly_dq_bitslip_rst_write(1);
}
int write_dq_bitslip[SDRAM_PHY_MODULES];
void write_inc_dq_bitslip(int module) {
/* Increment bitslip */
write_dq_bitslip[module] = (write_dq_bitslip[module] + 1) & (SDRAM_PHY_BITSLIPS - 1);
ddrphy_wdly_dq_bitslip_write(1);
}
void write_rst_dq_bitslip(int module) {
/* Increment bitslip */
write_dq_bitslip[module] = 0;
ddrphy_wdly_dq_bitslip_rst_write(1);
}
#endif // defined(SDRAM_PHY_BITSLIPS)
void sdram_select(int module, int dq_line) {
ddrphy_dly_sel_write(1 << module);
#ifdef SDRAM_DELAY_PER_DQ
/* Select DQ line */
ddrphy_dq_dly_sel_write(1 << dq_line);
#endif
}
void sdram_deselect(int module, int dq_line) {
ddrphy_dly_sel_write(0);
#if defined(SDRAM_PHY_ECP5DDRPHY) || defined(SDRAM_PHY_GW2DDRPHY)
/* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */
ddrphy_dly_sel_write(0xff);
ddrphy_dly_sel_write(0);
#endif //SDRAM_PHY_ECP5DDRPHY
#ifdef SDRAM_DELAY_PER_DQ
/* Un-select DQ line */
ddrphy_dq_dly_sel_write(0);
#endif
}
void sdram_leveling_action(int module, int dq_line, action_callback action) {
/* Select module */
sdram_select(module, dq_line);
/* Action */
action(module);
/* Un-select module */
sdram_deselect(module, dq_line);
}
#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
int _sdram_write_leveling_dat_delays[16];
void sdram_write_leveling_rst_dat_delay(int module, int show) {
_sdram_write_leveling_dat_delays[module] = -1;
if (show)
printf("Reseting Dat delay of module %d\n", module);
}
void sdram_write_leveling_force_dat_delay(int module, int taps, int show) {
_sdram_write_leveling_dat_delays[module] = taps;
if (show)
printf("Forcing Dat delay of module %d to %d taps\n", module, taps);
}
#if defined(SDRAM_PHY_BITSLIPS)
int _sdram_write_leveling_bitslips[16];
void sdram_write_leveling_rst_bitslip(int module, int show) {
_sdram_write_leveling_bitslips[module] = -1;
if (show)
printf("Reseting Bitslip of module %d\n", module);
}
void sdram_write_leveling_force_bitslip(int module, int bitslip, int show) {
_sdram_write_leveling_bitslips[module] = bitslip;
if (show)
printf("Forcing Bitslip of module %d to %d\n", module, bitslip);
}
#endif // defined(SDRAM_PHY_BITSLIPS)
#endif // SDRAM_PHY_WRITE_LEVELING_CAPABLE
#endif // defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)

74
litex/soc/software/liblitedram/accessors.h Normal file
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@ -0,0 +1,74 @@
#ifndef __ACCESSORS_H
#define __ACCESSORS_H
#ifdef __cplusplus
extern "C" {
#endif
#include <generated/csr.h>
#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
#include <generated/sdram_phy.h>
typedef void (*action_callback)(int module);
#if defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
extern int read_dq_delay[SDRAM_PHY_MODULES];
void read_inc_dq_delay(int module);
void read_rst_dq_delay(int module);
#endif // defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
#if defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE)
extern int sdram_clock_delay;
void sdram_inc_clock_delay(void);
void sdram_rst_clock_delay(void);
extern int write_dq_delay[SDRAM_PHY_MODULES];
void write_inc_dq_delay(int module);
void write_rst_dq_delay(int module);
void write_inc_dqs_delay(int module);
void write_rst_dqs_delay(int module);
void write_inc_delay(int module);
void write_rst_delay(int module);
#endif // defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE)
#if defined(SDRAM_PHY_BITSLIPS)
extern int read_dq_bitslip[SDRAM_PHY_MODULES];
void read_inc_dq_bitslip(int module);
void read_rst_dq_bitslip(int module);
extern int write_dq_bitslip[SDRAM_PHY_MODULES];
void write_inc_dq_bitslip(int module);
void write_rst_dq_bitslip(int module);
#endif // defined(SDRAM_PHY_BITSLIPS)
void sdram_select(int module, int dq_line);
void sdram_deselect(int module, int dq_line);
void sdram_leveling_action(int module, int dq_line, action_callback action);
#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
extern int _sdram_write_leveling_dat_delays[16];
void sdram_write_leveling_rst_dat_delay(int module, int show);
void sdram_write_leveling_force_dat_delay(int module, int taps, int show);
#if defined(SDRAM_PHY_BITSLIPS)
extern int _sdram_write_leveling_bitslips[16];
void sdram_write_leveling_rst_bitslip(int module, int show);
void sdram_write_leveling_force_bitslip(int module, int bitslip, int show);
#endif // defined(SDRAM_PHY_BITSLIPS)
#endif // SDRAM_PHY_WRITE_LEVELING_CAPABLE
#endif // defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
#ifdef __cplusplus
}
#endif
#endif // __ACCESSORS_H

961
litex/soc/software/liblitedram/sdram.c
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4
litex/soc/software/liblitedram/sdram.h
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@ -31,10 +31,6 @@ void sdram_mode_register_write(char reg, int value);
/*-----------------------------------------------------------------------*/
void sdram_write_leveling_rst_cmd_delay(int show);
void sdram_write_leveling_force_cmd_delay(int taps, int show);
void sdram_write_leveling_rst_dat_delay(int module, int show);
void sdram_write_leveling_force_dat_delay(int module, int taps, int show);
void sdram_write_leveling_rst_bitslip(int module, int show);
void sdram_write_leveling_force_bitslip(int module, int bitslip, int show);
int sdram_write_leveling(void);
/*-----------------------------------------------------------------------*/