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Merge pull request #432 from esden/csr-doc-fix-int 

Don't let python convert lane number to float.
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Sean Cross 2020-03-20 09:20:02 +08:00 committed by GitHub
parent dd07a0ad2f 279886721b
commit fbadfa1764
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1 changed files with 5 additions and 4 deletions
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9
litex/soc/doc/csr.py
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@ -257,8 +257,8 @@ class DocumentedCSRRegion:
print(" {\"name\": \"" + field_name + "\", " + type_str + attr_str + "\"bits\": " + str(field.size) + "}" + term, file=stream)
bit_offset = field.offset + field.size
min_field_size = min(min_field_size, field.size)
if min_field_size < 8:
multilane = True
if min_field_size < 8:
multilane = True
if bit_offset != self.busword:
print(" {\"bits\": " + str(self.busword - bit_offset) + "}", file=stream)
else:
@ -270,10 +270,11 @@ class DocumentedCSRRegion:
attr_str = "\"attr\": 'reset: " + str(reg.reset_value) + "', "
print(" {\"name\": \"" + reg.short_name.lower() + self.bit_range(reg.offset, reg.offset + reg.size, empty_if_zero=True) + "\", " + attr_str + "\"bits\": " + str(reg.size) + "}" + term, file=stream)
if reg.size != self.csr_data_width:
multilane = True
print(" {\"bits\": " + str(self.csr_data_width - reg.size) + "},", file=stream)
if reg.size < 8:
multilane = True
if multilane:
lanes = self.busword / 8
lanes = self.busword // 8
else:
lanes = 1
print(" ], \"config\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": " + str(lanes) + " }, \"options\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": " + str(lanes) + "}", file=stream)