examples: demonstrate multi-clock support

This commit is contained in:
Sebastien Bourdeauducq 2012-09-10 23:46:19 +02:00
parent f7b1e67d08
commit fc3187317b
2 changed files with 24 additions and 1 deletions

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@ -15,7 +15,7 @@ p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8)
a2 = Signal(BV(d_b))
d2 = Signal(BV(w))
re2 = Signal()
p2 = MemoryPort(a2, d2, re=re2)
p2 = MemoryPort(a2, d2, re=re2, clock_domain="rd")
mem = Memory(w, d, p1, p2, init=[5, 18, 32])
f = Fragment(memories=[mem])

23
examples/basic/psync.py Normal file
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@ -0,0 +1,23 @@
from migen.fhdl.structure import *
from migen.fhdl import verilog
# convert pulse into level change
i = Signal()
level = Signal()
isync = [If(i, level.eq(~level))]
# synchronize level to oclk domain
slevel = [Signal() for i in range(3)]
osync = [
slevel[0].eq(level),
slevel[1].eq(slevel[0]),
slevel[2].eq(slevel[1])
]
# regenerate pulse
o = Signal()
comb = [o.eq(slevel[1] ^ slevel[2])]
f = Fragment(comb, {"i": isync, "o": osync})
v = verilog.convert(f, ios={i, o})
print(v)