mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
fill GTXE2_CHANNEL constants parameters and signals for SATA / disconnect unused output ports
This commit is contained in:
Florent Kermarrec
parent
ac8d8783cf
commit
fc64b44391
1 changed files with 349 additions and 360 deletions
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@ -1,320 +1,314 @@
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class K7SATAPHY(Module):
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def __init__(self):
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_K28_5 = 0b1010000011
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def _ones(width):
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return 2**width-1
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self.specials += \
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Instance("GTXE2_CHANNEL",
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# Simulation-Only Attributes
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p_SIM_RECEIVER_DETECT_PASS=,
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p_SIM_TX_EIDLE_DRIVE_LEVEL=,
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p_SIM_RESET_SPEEDUP=,
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p_SIM_RECEIVER_DETECT_PASS="TRUE",
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p_SIM_TX_EIDLE_DRIVE_LEVEL="X",
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p_SIM_RESET_SPEEDUP=,
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p_SIM_CPLLREFCLK_SEL=,
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p_SIM_VERSION=,
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# RX Byte and Word Alignment Attributes
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p_ALIGN_COMMA_DOUBLE=,
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p_ALIGN_COMMA_ENABLE=,
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p_ALIGN_COMMA_WORD=,
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p_ALIGN_MCOMMA_DET=,
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p_ALIGN_MCOMMA_VALUE=,
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p_ALIGN_PCOMMA_DET=,
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p_ALIGN_PCOMMA_VALUE=,
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p_SHOW_REALIGN_COMMA=,
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p_RXSLIDE_AUTO_WAIT=,
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p_RXSLIDE_MODE=,
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p_RX_SIG_VALID_DLY=,
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p_ALIGN_COMMA_DOUBLE="FALSE",
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p_ALIGN_COMMA_ENABLE=_ones(10),
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p_ALIGN_COMMA_WORD=2,
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p_ALIGN_MCOMMA_DET="TRUE",
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p_ALIGN_MCOMMA_VALUE=_K28_5,
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p_ALIGN_PCOMMA_DET="TRUE",
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p_ALIGN_PCOMMA_VALUE=~_K28_5,
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p_SHOW_REALIGN_COMMA="FALSE",
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p_RXSLIDE_AUTO_WAIT=7,
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p_RXSLIDE_MODE="OFF",
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p_RX_SIG_VALID_DLY=10,
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# RX 8B/10B Decoder Attributes
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p_RX_DISPERR_SEQ_MATCH=,
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p_DEC_MCOMMA_DETECT=,
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p_DEC_PCOMMA_DETECT=,
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p_DEC_VALID_COMMA_ONLY=,
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p_RX_DISPERR_SEQ_MATCH="TRUE",
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p_DEC_MCOMMA_DETECT="TRUE",
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p_DEC_PCOMMA_DETECT="TRUE",
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p_DEC_VALID_COMMA_ONLY="FALSE",
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# RX Clock Correction Attributes
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p_CBCC_DATA_SOURCE_SEL=,
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p_CLK_COR_SEQ_2_USE=,
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p_CLK_COR_SEQ_2_USE=,
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p_CLK_COR_KEEP_IDLE=,
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p_CLK_COR_MAX_LAT=,
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p_CLK_COR_MIN_LAT=,
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p_CLK_COR_PRECEDENCE=,
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p_CLK_COR_REPEAT_WAIT=,
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p_CLK_COR_SEQ_LEN=,
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p_CLK_COR_SEQ_1_ENABLE=,
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p_CLK_COR_SEQ_1_ENABLE=,
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p_CLK_COR_SEQ_1_1=,
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p_CLK_COR_SEQ_1_1=,
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p_CLK_COR_SEQ_1_2=,
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p_CBCC_DATA_SOURCE_SEL="DECODED",
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p_CLK_COR_SEQ_2_USE="FALSE",
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p_CLK_COR_KEEP_IDLE="FALSE",
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p_CLK_COR_MAX_LAT=9,
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p_CLK_COR_MIN_LAT=7,
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p_CLK_COR_PRECEDENCE="TRUE",
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p_CLK_COR_REPEAT_WAIT=0,
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p_CLK_COR_SEQ_LEN=1,
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p_CLK_COR_SEQ_1_ENABLE=_ones(4),
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p_CLK_COR_SEQ_1_ENABLE=0,
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p_CLK_COR_SEQ_1_1=0,
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p_CLK_COR_SEQ_1_1=0,
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p_CLK_COR_SEQ_1_2=0,
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p_CLK_COR_SEQ_1_3=,
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p_CLK_COR_SEQ_1_4=,
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p_CLK_CORRECT_USE=,
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p_CLK_CORRECT_USE=,
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p_CLK_COR_SEQ_2_ENABLE=,
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p_CLK_COR_SEQ_2_ENABLE=,
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p_CLK_COR_SEQ_2_1=,
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p_CLK_COR_SEQ_2_1=,
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p_CLK_COR_SEQ_2_2=,
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p_CLK_COR_SEQ_2_3=,
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p_CLK_COR_SEQ_2_4=,
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p_CLK_COR_SEQ_1_4=0,
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p_CLK_CORRECT_USE="FALSE",
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p_CLK_COR_SEQ_2_ENABLE=_ones(4),
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p_CLK_COR_SEQ_2_1=0,
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p_CLK_COR_SEQ_2_2=0,
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p_CLK_COR_SEQ_2_3=0,
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p_CLK_COR_SEQ_2_4=0,
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# RX Channel Bonding Attributes
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p_CHAN_BOND_KEEP_ALIGN=,
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p_CHAN_BOND_MAX_SKEW=,
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p_CHAN_BOND_SEQ_LEN=,
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p_CHAN_BOND_SEQ_1_1=,
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p_CHAN_BOND_SEQ_1_1=,
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p_CHAN_BOND_SEQ_1_2=,
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p_CHAN_BOND_SEQ_1_3=,
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p_CHAN_BOND_SEQ_1_4=,
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p_CHAN_BOND_SEQ_1_ENABLE=,
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p_CHAN_BOND_SEQ_1_ENABLE=,
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p_CHAN_BOND_SEQ_2_1=,
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p_CHAN_BOND_SEQ_2_2=,
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p_CHAN_BOND_SEQ_2_3=,
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p_CHAN_BOND_SEQ_2_4=,
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p_CHAN_BOND_SEQ_2_ENABLE=,
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p_CHAN_BOND_SEQ_2_ENABLE=,
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p_CHAN_BOND_SEQ_2_USE=,
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p_FTS_DESKEW_SEQ_ENABLE=,
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p_FTS_LANE_DESKEW_CFG=,
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p_FTS_LANE_DESKEW_EN=,
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p_CHAN_BOND_KEEP_ALIGN="FALSE",
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p_CHAN_BOND_MAX_SKEW=1,
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p_CHAN_BOND_SEQ_LEN=1,
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p_CHAN_BOND_SEQ_1_1=0,
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p_CHAN_BOND_SEQ_1_1=0,
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p_CHAN_BOND_SEQ_1_2=0,
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p_CHAN_BOND_SEQ_1_3=0,
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p_CHAN_BOND_SEQ_1_4=0,
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p_CHAN_BOND_SEQ_1_ENABLE=_ones(4),
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p_CHAN_BOND_SEQ_2_1=0,
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p_CHAN_BOND_SEQ_2_2=0,
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p_CHAN_BOND_SEQ_2_3=0,
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p_CHAN_BOND_SEQ_2_4=0,
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p_CHAN_BOND_SEQ_2_ENABLE=_ones(4),
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p_CHAN_BOND_SEQ_2_USE="FALSE",
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p_FTS_DESKEW_SEQ_ENABLE=_ones(4),
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p_FTS_LANE_DESKEW_CFG=_ones(4),
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p_FTS_LANE_DESKEW_EN="FALSE",
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# RX Margin Analysis Attributes
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p_ES_CONTROL=,
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p_ES_ERRDET_EN=,
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p_ES_EYE_SCAN_EN=,
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p_ES_HORZ_OFFSET=,
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p_ES_PMA_CFG=,
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p_ES_PRESCALE=,
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p_ES_QUALIFIER=,
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p_ES_QUAL_MASK=,
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p_ES_SDATA_MASK=,
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p_ES_VERT_OFFSET=,
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p_ES_CONTROL=0,
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p_ES_ERRDET_EN="FALSE",
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p_ES_EYE_SCAN_EN="TRUE",
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p_ES_HORZ_OFFSET=0,
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p_ES_PMA_CFG=0,
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p_ES_PRESCALE=0,
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p_ES_QUALIFIER=0,
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p_ES_QUAL_MASK=0,
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p_ES_SDATA_MASK=0,
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p_ES_VERT_OFFSET=0,
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# FPGA RX Interface Attributes
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p_RX_DATA_WIDTH=,
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p_RX_DATA_WIDTH=20,
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# PMA Attributes
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p_OUTREFCLK_SEL_INV=,
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p_OUTREFCLK_SEL_INV=0b11,
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p_PMA_RSV=,
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p_PMA_RSV2=,
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p_PMA_RSV3=,
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p_PMA_RSV4=,
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p_RX_BIAS_CFG=,
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p_DMONITOR_CFG=,
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p_RX_CM_SEL=,
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p_RX_CM_TRIM=,
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p_RX_DEBUG_CFG=,
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p_RX_OS_CFG=,
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p_TERM_RCAL_CFG=,
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p_TERM_RCAL_OVRD=,
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p_TST_RSV=,
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p_RX_CLK25_DIV=,
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p_TX_CLK25_DIV=,
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p_UCODEER_CLR=,
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p_PMA_RSV2=0x2050,
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p_PMA_RSV3=0,
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p_PMA_RSV4=0,
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p_RX_BIAS_CFG=0b100,
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p_DMONITOR_CFG=0xA00,
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p_RX_CM_SEL=0b11,
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p_RX_CM_TRIM=0b010,
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p_RX_DEBUG_CFG=0,
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p_RX_OS_CFG=0b10000000,
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p_TERM_RCAL_CFG=0,
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p_TERM_RCAL_OVRD=0,
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p_TST_RSV=0,
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p_RX_CLK25_DIV=6,
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p_TX_CLK25_DIV=6,
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p_UCODEER_CLR=0,
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# PCI Express Attributes
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p_PCS_PCIE_EN=,
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p_PCS_PCIE_EN="FALSE",
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# PCS Attributes
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p_PCS_RSVD_ATTR=,
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# RX Buffer Attributes
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p_RXBUF_ADDR_MODE=,
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p_RXBUF_ADDR_MODE=,
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p_RXBUF_EIDLE_HI_CNT=,
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p_RXBUF_EIDLE_LO_CNT=,
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p_RXBUF_EN=,
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p_RX_BUFFER_CFG=,
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p_RXBUF_RESET_ON_CB_CHANGE=,
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p_RXBUF_RESET_ON_COMMAALIGN=,
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p_RXBUF_RESET_ON_EIDLE=,
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p_RXBUF_RESET_ON_RATE_CHANGE=,
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p_RXBUFRESET_TIME=,
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p_RXBUF_THRESH_OVFLW=,
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p_RXBUF_THRESH_OVRD=,
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p_RXBUF_THRESH_UNDFLW=,
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p_RXDLY_CFG=,
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p_RXDLY_LCFG=,
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p_RXDLY_TAP_CFG=,
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p_RXPH_CFG=,
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p_RXPHDLY_CFG=,
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p_RXPH_MONITOR_SEL=,
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p_RX_XCLK_SEL=,
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p_RX_DDI_SEL=,
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p_RX_DEFER_RESET_BUF_EN=,
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p_RXBUF_ADDR_MODE="FAST",
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p_RXBUF_EIDLE_HI_CNT=0b1000,
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p_RXBUF_EIDLE_LO_CNT=0,
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p_RXBUF_EN="FALSE",
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p_RX_BUFFER_CFG=0,
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p_RXBUF_RESET_ON_CB_CHANGE="TRUE",
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p_RXBUF_RESET_ON_COMMAALIGN="FALSE",
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p_RXBUF_RESET_ON_EIDLE="FALSE",
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p_RXBUF_RESET_ON_RATE_CHANGE="TRUE",
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p_RXBUFRESET_TIME=1,
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p_RXBUF_THRESH_OVFLW=61,
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p_RXBUF_THRESH_OVRD="FALSE",
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p_RXBUF_THRESH_UNDFLW=4,
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p_RXDLY_CFG=0x1f,
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p_RXDLY_LCFG=0x30,
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p_RXDLY_TAP_CFG=0,
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p_RXPH_CFG=0,
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p_RXPHDLY_CFG=0x084820,
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p_RXPH_MONITOR_SEL=0,
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p_RX_XCLK_SEL="RXUSR",
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p_RX_DDI_SEL=0,
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p_RX_DEFER_RESET_BUF_EN="TRUE",
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#CDR Attributes
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#Gen 3, 6 Gb/s 1 72'h03_8000_8BFF_1020_0010
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#Gen 2, 3 Gb/s 2 72'h03_8800_8BFF_4020_0008
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#Gen 1, 1.5 Gb/s 4 72'h03_8000_8BFF_4010_0008
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p_RXCDR_CFG=,
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p_RXCDR_FR_RESET_ON_EIDLE=,
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p_RXCDR_HOLD_DURING_EIDLE=,
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p_RXCDR_PH_RESET_ON_EIDLE=,
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p_RXCDR_LOCK_CFG=,
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p_RXCDR_FR_RESET_ON_EIDLE=0,
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p_RXCDR_HOLD_DURING_EIDLE=0,
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p_RXCDR_PH_RESET_ON_EIDLE=0,
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p_RXCDR_LOCK_CFG=0b010101,
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# RX Initialization and Reset Attributes
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p_RXCDRFREQRESET_TIME=,
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p_RXCDRPHRESET_TIME=,
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p_RXISCANRESET_TIME=,
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p_RXPCSRESET_TIME=,
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p_RXPMARESET_TIME=,
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p_RXCDRFREQRESET_TIME=1,
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p_RXCDRPHRESET_TIME=1,
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p_RXISCANRESET_TIME=1,
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p_RXPCSRESET_TIME=1,
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p_RXPMARESET_TIME=3,
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# RX OOB Signaling Attributes
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p_RXOOB_CFG=,
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p_RXOOB_CFG=0b0000110,
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# RX Gearbox Attributes
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p_RXGEARBOX_EN=,
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p_GEARBOX_MODE=,
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p_RXGEARBOX_EN="FALSE",
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p_GEARBOX_MODE=0,
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# PRBS Detection Attribute
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p_RXPRBS_ERR_LOOPBACk=,
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p_RXPRBS_ERR_LOOPBACK=0,
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# Power-Down Attributes
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p_PD_TRANS_TIME_FROM_P2=,
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p_PD_TRANS_TIME_NONE_P2=,
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p_PD_TRANS_TIME_TO_P2=,
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p_PD_TRANS_TIME_FROM_P2=0x03c,
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p_PD_TRANS_TIME_NONE_P2=0x3c,
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p_PD_TRANS_TIME_TO_P2=0x64,
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# RX OOB Signaling Attributes
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p_SAS_MAX_COM=,
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p_SAS_MIN_COM=,
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p_SATA_BURST_SEQ_LEN=,
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p_SATA_BURST_SEQ_LEN=,
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p_SATA_BURST_VAL=,
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p_SATA_EIDLE_VAL=,
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p_SATA_MAX_BURST=,
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p_SATA_MAX_INIT=,
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p_SATA_MAX_WAKE=,
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p_SATA_MIN_BURST=,
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p_SATA_MIN_INIT=,
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p_SATA_MIN_WAKE=,
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p_SAS_MAX_COM=64,
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p_SAS_MIN_COM=36,
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p_SATA_BURST_SEQ_LEN=0b0101,
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p_SATA_BURST_VAL=0b100,
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p_SATA_EIDLE_VAL=0b100,
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p_SATA_MAX_BURST=8,
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p_SATA_MAX_INIT=21,
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p_SATA_MAX_WAKE=7,
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p_SATA_MIN_BURST=4,
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p_SATA_MIN_INIT=12,
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p_SATA_MIN_WAKE=4,
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# RX Fabric Clock Output Control Attributes
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p_TRANS_TIME_RATE=,
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p_TRANS_TIME_RATE=0x0e,
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# TX Buffer Attributes
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p_TXBUF_EN=,
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p_TXBUF_EN=,
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p_TXBUF_RESET_ON_RATE_CHANGE=,
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p_TXDLY_CFG=,
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p_TXDLY_LCFG=,
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p_TXDLY_TAP_CFG=,
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p_TXPH_CFG=,
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p_TXPHDLY_CFG=,
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p_TXPH_MONITOR_SEL=,
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p_TX_XCLK_SEL=,
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p_TX_XCLK_SEL=,
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p_TXBUF_EN="FALSE",
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p_TXBUF_RESET_ON_RATE_CHANGE="FALSE",
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p_TXDLY_CFG=0x1f,
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p_TXDLY_LCFG=0x030,
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p_TXDLY_TAP_CFG=0,
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p_TXPH_CFG=0x0780,
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p_TXPHDLY_CFG=0x084020,
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p_TXPH_MONITOR_SEL=0,
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p_TX_XCLK_SEL="TXUSR",
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# FPGA TX Interface Attributes
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p_TX_DATA_WIDTH=,
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p_TX_DATA_WIDTH=20,
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# TX Configurable Driver Attributes
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p_TX_DEEMPH0=,
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p_TX_DEEMPH1=,
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p_TX_EIDLE_ASSERT_DELAY=,
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p_TX_EIDLE_DEASSERT_DELAY=,
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p_TX_LOOPBACK_DRIVE_HIZ=,
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p_TX_MAINCURSOR_SEL=,
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p_TX_DRIVE_MODE=,
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p_TX_MARGIN_FULL_0=,
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p_TX_MARGIN_FULL_1=,
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p_TX_MARGIN_FULL_2=,
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p_TX_MARGIN_FULL_3=,
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p_TX_MARGIN_FULL_4=,
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p_TX_MARGIN_LOW_0=,
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p_TX_MARGIN_LOW_1=,
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p_TX_MARGIN_LOW_2=,
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p_TX_MARGIN_LOW_3=,
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p_TX_MARGIN_LOW_4=,
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p_TX_DEEMPH0=0,
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p_TX_DEEMPH1=0,
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p_TX_EIDLE_ASSERT_DELAY=0b110,
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p_TX_EIDLE_DEASSERT_DELAY=0b100,
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p_TX_LOOPBACK_DRIVE_HIZ="FALSE",
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p_TX_MAINCURSOR_SEL=0,
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p_TX_DRIVE_MODE="DIRECT",
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p_TX_MARGIN_FULL_0=0b1001110,
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p_TX_MARGIN_FULL_1=0b1001001,
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p_TX_MARGIN_FULL_2=0b1000101,
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p_TX_MARGIN_FULL_3=0b1000010,
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p_TX_MARGIN_FULL_4=0b1000000,
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p_TX_MARGIN_LOW_0=0b1000110,
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p_TX_MARGIN_LOW_1=0b1000100,
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p_TX_MARGIN_LOW_2=0b1000010,
|
||||
p_TX_MARGIN_LOW_3=0b1000000,
|
||||
p_TX_MARGIN_LOW_4=0b1000000,
|
||||
|
||||
# TX Gearbox Attributes
|
||||
p_TXGEARBOX_EN=,
|
||||
p_TXGEARBOX_EN="FALSE",
|
||||
|
||||
# TX Initialization and Reset Attributes
|
||||
p_TXPCSRESET_TIME=,
|
||||
p_TXPMARESET_TIME=,
|
||||
p_TXPCSRESET_TIME=1,
|
||||
p_TXPMARESET_TIME=1,
|
||||
|
||||
# TX Receiver Detection Attributes
|
||||
p_TX_RXDETECT_CFG=,
|
||||
p_TX_RXDETECT_REF=,
|
||||
p_TX_RXDETECT_CFG=0x1832,
|
||||
p_TX_RXDETECT_REF=0b100,
|
||||
|
||||
# CPLL Attributes
|
||||
p_CPLL_CFG=,
|
||||
p_CPLL_FBDIV=,
|
||||
p_CPLL_FBDIV_45=,
|
||||
p_CPLL_INIT_CFG=,
|
||||
p_CPLL_LOCK_CFG=,
|
||||
p_CPLL_REFCLK_DIV=,
|
||||
p_CPLL_CFG=0xBC07DC,
|
||||
p_CPLL_FBDIV=4,
|
||||
p_CPLL_FBDIV_45=5,
|
||||
p_CPLL_INIT_CFG=0x00001E
|
||||
p_CPLL_LOCK_CFG=0x01e8,
|
||||
p_CPLL_REFCLK_DIV=1,
|
||||
p_RXOUT_DIV=,
|
||||
p_TXOUT_DIV=,
|
||||
p_RXOUT_DIV=,
|
||||
p_TXOUT_DIV=,
|
||||
p_SATA_CPLL_CFG=,
|
||||
p_SATA_CPLL_CFG="VCO_3000MHZ",
|
||||
|
||||
# RX Initialization and Reset Attributes
|
||||
p_RXDFELPMRESET_TIME=,
|
||||
p_RXDFELPMRESET_TIME=0b0001111,
|
||||
|
||||
# RX Equalizer Attributes
|
||||
p_RXLPM_HF_CFG=,
|
||||
p_RXLPM_LF_CFG=,
|
||||
p_RX_DFE_GAIN_CFG=,
|
||||
p_RX_DFE_H2_CFG=,
|
||||
p_RX_DFE_H3_CFG=,
|
||||
p_RX_DFE_H4_CFG=,
|
||||
p_RX_DFE_H5_CFG=,
|
||||
p_RX_DFE_KL_CFG=,
|
||||
p_RX_DFE_LPM_CFG=,
|
||||
p_RX_DFE_LPM_HOLD_DURING_EIDLE=,
|
||||
p_RX_DFE_UT_CFG=,
|
||||
p_RX_DFE_VP_CFG=,
|
||||
p_RXLPM_HF_CFG=0b00000011110000,
|
||||
p_RXLPM_LF_CFG=0b00000011110000,
|
||||
p_RX_DFE_GAIN_CFG=0b020FEA,
|
||||
p_RX_DFE_H2_CFG=0b000000000000,
|
||||
p_RX_DFE_H3_CFG=0b000001000000,
|
||||
p_RX_DFE_H4_CFG=0b00011110000,
|
||||
p_RX_DFE_H5_CFG=0b00011100000,
|
||||
p_RX_DFE_KL_CFG=0b0000011111110,
|
||||
p_RX_DFE_LPM_CFG=0x0954,
|
||||
p_RX_DFE_LPM_HOLD_DURING_EIDLE=1,
|
||||
p_RX_DFE_UT_CFG=0b10001111000000000,
|
||||
p_RX_DFE_VP_CFG=0b00011111100000011,
|
||||
|
||||
# Power-Down Attributes
|
||||
p_RX_CLKMUX_PD=,
|
||||
p_TX_CLKMUX_PD=,
|
||||
p_RX_CLKMUX_PD=1,
|
||||
p_TX_CLKMUX_PD=1,
|
||||
|
||||
# FPGA RX Interface Attribute
|
||||
p_RX_INT_DATAWIDTH=,
|
||||
p_RX_INT_DATAWIDTH=0,
|
||||
|
||||
# FPGA TX Interface Attribute
|
||||
p_TX_INT_DATAWIDTH=,
|
||||
p_TX_INT_DATAWIDTH=0,
|
||||
|
||||
# TX Configurable Driver Attributes
|
||||
p_TX_QPI_STATUS_EN=,
|
||||
p_TX_QPI_STATUS_EN=0,
|
||||
|
||||
# RX Equalizer Attributes
|
||||
p_RX_DFE_KL_CFG2=,
|
||||
p_RX_DFE_XYD_CFG=,
|
||||
p_RX_DFE_KL_CFG2=0b00110011000100000001100000001100
|
||||
p_RX_DFE_XYD_CFG=0bb0000000000000,
|
||||
|
||||
# TX Configurable Driver Attributes
|
||||
p_TX_PREDRIVER_MODE=,
|
||||
p_TX_PREDRIVER_MODE=0,
|
||||
|
||||
# CPLL Ports
|
||||
o_CPLLFBCLKLOST=,
|
||||
o_CPLLLOCK=,
|
||||
i_CPLLLOCKDETCLK=,
|
||||
i_CPLLLOCKDETCLK=,
|
||||
i_CPLLLOCKEN=,
|
||||
i_CPLLPD=,
|
||||
i_CPLLLOCKEN=1,
|
||||
i_CPLLPD=0,
|
||||
o_CPLLREFCLKLOST=,
|
||||
i_CPLLREFCLKSEL=,
|
||||
i_CPLLREFCLKSEL=0b001,
|
||||
i_CPLLRESET=,
|
||||
i_GTRSVD=,
|
||||
i_PCSRSVDIN=,
|
||||
i_PCSRSVDIN2=,
|
||||
i_PMARSVDIN=,
|
||||
i_PMARSVDIN2=,
|
||||
i_TSTIN=,
|
||||
o_TSTOUT=,
|
||||
i_PCSRSVDIN=0,
|
||||
i_PCSRSVDIN2=0,
|
||||
i_PMARSVDIN=0,
|
||||
i_PMARSVDIN2=0,
|
||||
i_TSTIN=_ones(20),
|
||||
#o_TSTOUT=,
|
||||
|
||||
# Channel
|
||||
i_CLKRSVD=,
|
||||
|
||||
# Channel - Clocking Ports
|
||||
i_GTGREFCLK=,
|
||||
i_GTNORTHREFCLK0=,
|
||||
i_GTNORTHREFCLK1=,
|
||||
i_GTGREFCLK=0,
|
||||
i_GTNORTHREFCLK0=0,
|
||||
i_GTNORTHREFCLK1=0,
|
||||
i_GTREFCLK0=,
|
||||
i_GTREFCLK1=,
|
||||
i_GTSOUTHREFCLK0=,
|
||||
i_GTSOUTHREFCLK1=,
|
||||
i_GTREFCLK1=0,
|
||||
i_GTSOUTHREFCLK0=0,
|
||||
i_GTSOUTHREFCLK1=0,
|
||||
|
||||
# Channel - DRP Ports
|
||||
i_DRPADDR=,
|
||||
|
|
@ -326,58 +320,57 @@ class K7SATAPHY(Module):
|
|||
i_DRPWE=,
|
||||
|
||||
# Clocking Ports
|
||||
o_GTREFCLKMONITOR=,
|
||||
#o_GTREFCLKMONITOR=,
|
||||
i_QPLLCLK=,
|
||||
i_QPLLCLK=,
|
||||
i_QPLLREFCLK=,
|
||||
i_QPLLREFCLK=,
|
||||
i_RXSYSCLKSEL=,
|
||||
i_TXSYSCLKSEL=,
|
||||
i_RXSYSCLKSEL=0b00,
|
||||
i_TXSYSCLKSEL=0b00,
|
||||
|
||||
# Digital Monitor Ports
|
||||
o_DMONITOROUT=,
|
||||
|
||||
# FPGA TX Interface Datapath Configuration
|
||||
i_TX8B10BEN=,
|
||||
i_TX8B10BEN=1,
|
||||
|
||||
# Loopback Ports
|
||||
i_LOOPBACK=,
|
||||
i_LOOPBACK=0,
|
||||
|
||||
# PCI Express Ports
|
||||
o_PHYSTATUS=,
|
||||
#o_PHYSTATUS=,
|
||||
i_RXRATE=,
|
||||
o_RXVALID=,
|
||||
#o_RXVALID=,
|
||||
|
||||
# Power-Down Ports
|
||||
i_RXPD=,
|
||||
i_TXPD=,
|
||||
i_RXPD=0b00,
|
||||
i_TXPD=0b00,
|
||||
|
||||
# RX 8B/10B Decoder Ports
|
||||
i_SETERRSTATUS=,
|
||||
i_SETERRSTATUS=0,
|
||||
|
||||
# RX Initialization and Reset Ports
|
||||
i_EYESCANRESET=,
|
||||
i_EYESCANRESET=0,
|
||||
i_RXUSERRDY=,
|
||||
|
||||
# RX Margin Analysis Ports
|
||||
o_EYESCANDATAERROR=,
|
||||
i_EYESCANMODE=,
|
||||
i_EYESCANTRIGGER=,
|
||||
i_EYESCANMODE=0,
|
||||
i_EYESCANTRIGGER=0,
|
||||
|
||||
# Receive Ports - CDR Ports
|
||||
i_RXCDRFREQRESET=,
|
||||
i_RXCDRHOLD=,
|
||||
i_RXCDRHOLD=0,
|
||||
o_RXCDRLOCK=,
|
||||
o_RXCDRLOCK=,
|
||||
i_RXCDROVRDEN=,
|
||||
i_RXCDRRESET=,
|
||||
i_RXCDRRESETRSV=,
|
||||
i_RXCDROVRDEN=0,
|
||||
i_RXCDRRESET=0,
|
||||
i_RXCDRRESETRSV=0,
|
||||
|
||||
# Receive Ports - Clock Correction Ports
|
||||
o_RXCLKCORCNT=,
|
||||
#o_RXCLKCORCNT=,
|
||||
|
||||
# Receive Ports - FPGA RX Interface Datapath Configuration
|
||||
i_RX8B10BEN=,
|
||||
i_RX8B10BEN=1,
|
||||
|
||||
# Receive Ports - FPGA RX Interface Ports
|
||||
i_RXUSRCLK=,
|
||||
|
|
@ -387,16 +380,16 @@ class K7SATAPHY(Module):
|
|||
i_RXDATA=,
|
||||
|
||||
# Receive Ports - Pattern Checker Ports
|
||||
o_RXPRBSERR=,
|
||||
i_RXPRBSSEL=,
|
||||
#o_RXPRBSERR=,
|
||||
i_RXPRBSSEL=0,
|
||||
|
||||
# Receive Ports - Pattern Checker ports
|
||||
i_RXPRBSCNTRESET=,
|
||||
i_RXPRBSCNTRESET=0,
|
||||
|
||||
# Receive Ports - RX Equalizer Ports
|
||||
i_RXDFEXYDEN=,
|
||||
i_RXDFEXYDHOLD=,
|
||||
i_RXDFEXYDOVRDEN=,
|
||||
i_RXDFEXYDEN=0,
|
||||
i_RXDFEXYDHOLD=0,
|
||||
i_RXDFEXYDOVRDEN=0,
|
||||
|
||||
# Receive Ports - RX 8B/10B Decoder Ports
|
||||
i_RXDISPERR=,
|
||||
|
|
@ -409,106 +402,104 @@ class K7SATAPHY(Module):
|
|||
i_GTXRXN=,
|
||||
|
||||
# Receive Ports - RX Buffer Bypass Ports
|
||||
i_RXBUFRESET=,
|
||||
o_RXBUFSTATUS=,
|
||||
i_RXDDIEN=,
|
||||
i_RXDLYBYPASS=,
|
||||
i_RXBUFRESET=0,
|
||||
#o_RXBUFSTATUS=,
|
||||
i_RXDDIEN=1,
|
||||
i_RXDLYBYPASS=0,
|
||||
i_RXDLYEN=,
|
||||
i_RXDLYOVRDEN=,
|
||||
i_RXDLYOVRDEN=0,
|
||||
i_RXDLYSRESET=,
|
||||
o_RXDLYSRESETDONE=,
|
||||
i_RXPHALIGN=,
|
||||
o_RXPHALIGNDONE=,
|
||||
i_RXPHALIGNEN=,
|
||||
i_RXPHDLYPD=,
|
||||
i_RXPHDLYPD=0,
|
||||
i_RXPHDLYRESET=,
|
||||
o_RXPHMONITOR=,
|
||||
i_RXPHOVRDEN=,
|
||||
i_RXPHOVRDEN=0,
|
||||
o_RXPHSLIPMONITOR=,
|
||||
o_RXSTATUS=,
|
||||
|
||||
# Receive Ports - RX Byte and Word Alignment Ports
|
||||
o_RXBYTEISALIGNED=,
|
||||
o_RXBYTEREALIGN=,
|
||||
o_RXCOMMADET=,
|
||||
i_RXCOMMADETEN=,
|
||||
#o_RXBYTEISALIGNED=,
|
||||
#o_RXBYTEREALIGN=,
|
||||
#o_RXCOMMADET=,
|
||||
i_RXCOMMADETEN=1,
|
||||
i_RXMCOMMAALIGNEN=,
|
||||
i_RXMCOMMAALIGNEN=,
|
||||
i_RXPCOMMAALIGNEN=,
|
||||
i_RXPCOMMAALIGNEN=,
|
||||
|
||||
# Receive Ports - RX Channel Bonding Ports
|
||||
o_RXCHANBONDSEQ=,
|
||||
i_RXCHBONDEN=,
|
||||
i_RXCHBONDLEVEL=,
|
||||
i_RXCHBONDMASTER=,
|
||||
o_RXCHBONDO=,
|
||||
i_RXCHBONDSLAVE=,
|
||||
#o_RXCHANBONDSEQ=,
|
||||
i_RXCHBONDEN=0,
|
||||
i_RXCHBONDLEVEL=0,
|
||||
i_RXCHBONDMASTER=0,
|
||||
#o_RXCHBONDO=,
|
||||
i_RXCHBONDSLAVE=0,
|
||||
|
||||
# Receive Ports - RX Channel Bonding Ports
|
||||
o_RXCHANISALIGNED=,
|
||||
o_RXCHANREALIGN=,
|
||||
#o_RXCHANISALIGNED=,
|
||||
#o_RXCHANREALIGN=,
|
||||
|
||||
# Receive Ports - RX Equalizer Ports
|
||||
i_RXDFEAGCHOLD=,
|
||||
i_RXDFEAGCOVRDEN=,
|
||||
i_RXDFECM1EN=,
|
||||
i_RXDFELFHOLD=,
|
||||
i_RXDFELFOVRDEN=,
|
||||
i_RXDFELPMRESET=,
|
||||
i_RXDFETAP2HOLD=,
|
||||
i_RXDFETAP2OVRDEN=,
|
||||
i_RXDFETAP3HOLD=,
|
||||
i_RXDFETAP3OVRDEN=,
|
||||
i_RXDFETAP4HOLD=,
|
||||
i_RXDFETAP4OVRDEN=,
|
||||
i_RXDFETAP5HOLD=,
|
||||
i_RXDFETAP5OVRDEN=,
|
||||
i_RXDFEUTHOLD=,
|
||||
i_RXDFEUTOVRDEN=,
|
||||
i_RXDFEVPHOLD=,
|
||||
i_RXDFEVPOVRDEN=,
|
||||
i_RXDFEVSEN=,
|
||||
i_RXLPMLFKLOVRDEN=,
|
||||
o_RXMONITOROUT=,
|
||||
i_RXMONITORSEL=,
|
||||
i_RXOSHOLD=,
|
||||
i_RXOSOVRDEN=,
|
||||
i_RXDFEAGCHOLD=0,
|
||||
i_RXDFEAGCOVRDEN=0,
|
||||
i_RXDFECM1EN=0,
|
||||
i_RXDFELFHOLD=0,
|
||||
i_RXDFELFOVRDEN=1,
|
||||
i_RXDFELPMRESET=0,
|
||||
i_RXDFETAP2HOLD=0,
|
||||
i_RXDFETAP2OVRDEN=0,
|
||||
i_RXDFETAP3HOLD=0,
|
||||
i_RXDFETAP3OVRDEN=0,
|
||||
i_RXDFETAP4HOLD=0,
|
||||
i_RXDFETAP4OVRDEN=0,
|
||||
i_RXDFETAP5HOLD=0,
|
||||
i_RXDFETAP5OVRDEN=0,
|
||||
i_RXDFEUTHOLD=0,
|
||||
i_RXDFEUTOVRDEN=0,
|
||||
i_RXDFEVPHOLD=0,
|
||||
i_RXDFEVPOVRDEN=0,
|
||||
i_RXDFEVSEN=0,
|
||||
i_RXLPMLFKLOVRDEN=0,
|
||||
#o_RXMONITOROUT=,
|
||||
i_RXMONITORSEL=0b00,
|
||||
i_RXOSHOLD=0,
|
||||
i_RXOSOVRDEN=0,
|
||||
|
||||
# Receive Ports - RX Equilizer Ports
|
||||
i_RXLPMHFHOLD=,
|
||||
i_RXLPMHFOVRDEN=,
|
||||
i_RXLPMLFHOLD=,
|
||||
i_RXLPMHFHOLD=0,
|
||||
i_RXLPMHFOVRDEN=0,
|
||||
i_RXLPMLFHOLD=0,
|
||||
|
||||
# Receive Ports - RX Fabric ClocK Output Control Ports
|
||||
o_RXRATEDONE=,
|
||||
|
||||
# Receive Ports - RX Fabric Output Control Ports
|
||||
o_RXOUTCLK=,
|
||||
o_RXOUTCLKFABRIC=,
|
||||
o_RXOUTCLKPCS=,
|
||||
i_RXOUTCLKSEL=,
|
||||
#o_RXOUTCLKFABRIC=,
|
||||
#o_RXOUTCLKPCS=,
|
||||
i_RXOUTCLKSEL=0b010,
|
||||
|
||||
# Receive Ports - RX Gearbox Ports
|
||||
o_RXDATAVALID=,
|
||||
o_RXHEADER=,
|
||||
o_RXHEADERVALID=,
|
||||
o_RXSTARTOFSEQ=,
|
||||
#o_RXDATAVALID=,
|
||||
#o_RXHEADER=,
|
||||
#o_RXHEADERVALID=,
|
||||
#o_RXSTARTOFSEQ=,
|
||||
|
||||
# Receive Ports - RX Gearbox Ports
|
||||
i_RXGEARBOXSLIP=,
|
||||
i_RXGEARBOXSLIP=0,
|
||||
|
||||
# Receive Ports - RX Initialization and Reset Ports
|
||||
i_GTRXRESET=,
|
||||
i_RXOOBRESET=,
|
||||
i_RXPCSRESET=,
|
||||
i_RXPMARESET=,
|
||||
i_RXOOBRESET=0,
|
||||
i_RXPCSRESET=0,
|
||||
i_RXPMARESET=0,
|
||||
|
||||
# Receive Ports - RX Margin Analysis ports
|
||||
i_RXLPMEN=,
|
||||
|
||||
# Receive Ports - RX OOB Signaling ports
|
||||
o_RXCOMSASDET=,
|
||||
#o_RXCOMSASDET=,
|
||||
o_RXCOMWAKEDET=,
|
||||
|
||||
# Receive Ports - RX OOB Signaling ports
|
||||
|
|
@ -519,44 +510,42 @@ class K7SATAPHY(Module):
|
|||
i_RXELECIDLEMODE=,
|
||||
|
||||
# Receive Ports - RX Polarity Control Ports
|
||||
i_RXPOLARITY=,
|
||||
i_RXPOLARITY=0,
|
||||
|
||||
# Receive Ports - RX gearbox ports
|
||||
i_RXSLIDE=,
|
||||
i_RXSLIDE=,
|
||||
i_RXSLIDE=0,
|
||||
|
||||
# Receive Ports - RX8B/10B Decoder Ports
|
||||
o_RXCHARISCOMMA=,
|
||||
#o_RXCHARISCOMMA=,
|
||||
o_RXCHARISK=,
|
||||
|
||||
# Receive Ports - Rx Channel Bonding Ports
|
||||
i_RXCHBONDI=,
|
||||
i_RXCHBONDI=0,
|
||||
|
||||
# Receive Ports -RX Initialization and Reset Ports
|
||||
o_RXRESETDONE=,
|
||||
|
||||
# Rx AFE Ports
|
||||
i_RXQPIEN=,
|
||||
o_RXQPISENN=,
|
||||
o_RXQPISENP=,
|
||||
i_RXQPIEN=0,
|
||||
#o_RXQPISENN=,
|
||||
#o_RXQPISENP=,
|
||||
|
||||
# TX Buffer Bypass Ports
|
||||
i_TXPHDLYTSTCL=,
|
||||
i_TXPHDLYTSTCLK=0,
|
||||
|
||||
# TX Configurable Driver Ports
|
||||
i_TXPOSTCURSOR=,
|
||||
i_TXPOSTCURSORINV=,
|
||||
i_TXPRECURSOR=,
|
||||
i_TXPRECURSOR=,
|
||||
i_TXPRECURSORINV=,
|
||||
i_TXQPIBIASEN=,
|
||||
i_TXQPISTRONGPDOWN=,
|
||||
i_TXQPIWEAKPUP=,
|
||||
i_TXPOSTCURSOR=0,
|
||||
i_TXPOSTCURSORINV=0,
|
||||
i_TXPRECURSOR=0,
|
||||
i_TXPRECURSORINV=0,
|
||||
i_TXQPIBIASEN=0,
|
||||
i_TXQPISTRONGPDOWN=0,
|
||||
i_TXQPIWEAKPUP=0,
|
||||
|
||||
# TX Initialization and Reset Ports
|
||||
i_CFGRESET=,
|
||||
i_GTTXRESET=,
|
||||
o_PCSRSVDOUT=,
|
||||
#o_PCSRSVDOUT=,
|
||||
i_TXUSERRDY=,
|
||||
|
||||
# Transceiver Reset Mode Operation
|
||||
|
|
@ -564,8 +553,8 @@ class K7SATAPHY(Module):
|
|||
i_RESETOVRD=,
|
||||
|
||||
# Transmit Ports - 8b10b Encoder Control Ports
|
||||
i_TXCHARDISPMODE=,
|
||||
i_TXCHARDISPVAL=,
|
||||
i_TXCHARDISPMODE=0,
|
||||
i_TXCHARDISPVAL=0,
|
||||
|
||||
# Transmit Ports - FPGA TX Interface Ports
|
||||
i_TXUSRCLK=,
|
||||
|
|
@ -573,41 +562,41 @@ class K7SATAPHY(Module):
|
|||
|
||||
# Transmit Ports - PCI Express Ports
|
||||
i_TXELECIDLE=,
|
||||
i_TXMARGIN=,
|
||||
i_TXMARGIN=0,
|
||||
i_TXRATE=,
|
||||
i_TXSWING=,
|
||||
i_TXSWING=0,
|
||||
|
||||
# Transmit Ports - Pattern Generator Ports
|
||||
i_TXPRBSFORCEERR=,
|
||||
i_TXPRBSFORCEERR=0,
|
||||
|
||||
# Transmit Ports - TX Buffer Bypass Ports
|
||||
i_TXDLYBYPASS=,
|
||||
i_TXDLYBYPASS=0,
|
||||
i_TXDLYEN=,
|
||||
i_TXDLYHOLD=,
|
||||
i_TXDLYOVRDEN=,
|
||||
i_TXDLYHOLD=0,
|
||||
i_TXDLYOVRDEN=0,
|
||||
i_TXDLYSRESET=,
|
||||
o_TXDLYSRESETDONE=,
|
||||
i_TXDLYUPDOWN=,
|
||||
i_TXDLYUPDOWN=0,
|
||||
i_TXPHALIGN=,
|
||||
o_TXPHALIGNDONE=,
|
||||
i_TXPHALIGNEN=,
|
||||
i_TXPHDLYPD=,
|
||||
i_TXPHDLYPD=0,
|
||||
i_TXPHDLYRESET=,
|
||||
i_TXPHINIT=,
|
||||
o_TXPHINITDONE=,
|
||||
i_TXPHOVRDEN=,
|
||||
i_TXPHOVRDEN=0,
|
||||
|
||||
# Transmit Ports - TX Buffer Ports
|
||||
o_TXBUFSTATUS=,
|
||||
#o_TXBUFSTATUS=,
|
||||
|
||||
# Transmit Ports - TX Configurable Driver Ports
|
||||
i_TXBUFDIFFCTRL=,
|
||||
i_TXDEEMPH=,
|
||||
i_TXDIFFCTRL=,
|
||||
i_TXDIFFPD=,
|
||||
i_TXINHIBIT=,
|
||||
i_TXMAINCURSOR=,
|
||||
i_TXPISOPD=,
|
||||
i_TXBUFDIFFCTRL=0b100,
|
||||
i_TXDEEMPH=0,
|
||||
i_TXDIFFCTRL=0b1000,
|
||||
i_TXDIFFPD=0,
|
||||
i_TXINHIBIT=0,
|
||||
i_TXMAINCURSOR=0,
|
||||
i_TXPISOPD=0,
|
||||
|
||||
# Transmit Ports - TX Data Path interface
|
||||
i_TXDATA=,
|
||||
|
|
@ -620,42 +609,42 @@ class K7SATAPHY(Module):
|
|||
o_TXOUTCLK=,
|
||||
o_TXOUTCLKFABRIC=,
|
||||
o_TXOUTCLKPCS=,
|
||||
i_TXOUTCLKSEL=,
|
||||
i_TXOUTCLKSEL=0b11,
|
||||
o_TXRATEDONE=,
|
||||
# Transmit Ports - TX Gearbox Ports
|
||||
i_TXCHARISK=,
|
||||
o_TXGEARBOXREADY=,
|
||||
i_TXHEADER=,
|
||||
i_TXSEQUENCE=,
|
||||
i_TXSTARTSEQ=,
|
||||
#o_TXGEARBOXREADY=,
|
||||
i_TXHEADER=0,
|
||||
i_TXSEQUENCE=0,
|
||||
i_TXSTARTSEQ=0,
|
||||
|
||||
# Transmit Ports - TX Initialization and Reset Ports
|
||||
i_TXPCSRESET=,
|
||||
i_TXPMARESET=,
|
||||
i_TXPCSRESET=0,
|
||||
i_TXPMARESET=0,
|
||||
o_TXRESETDONE=,
|
||||
|
||||
# Transmit Ports - TX OOB signalling Ports
|
||||
o_TXCOMFINISH=,
|
||||
i_TXCOMINIT=,
|
||||
i_TXCOMSAS=,
|
||||
i_TXCOMSAS=0,
|
||||
i_TXCOMWAKE=,
|
||||
i_TXPDELECIDLEMODE=,
|
||||
i_TXPDELECIDLEMODE=0,
|
||||
|
||||
# Transmit Ports - TX Polarity Control Ports
|
||||
i_TXPOLARITY=,
|
||||
i_TXPOLARITY=0,
|
||||
|
||||
# Transmit Ports - TX Receiver Detection Ports
|
||||
i_TXDETECTRX=,
|
||||
i_TXDETECTRX=0,
|
||||
|
||||
# Transmit Ports - TX8b/10b Encoder Ports
|
||||
i_TX8B10BBYPASS=
|
||||
i_TX8B10BBYPASS=0,
|
||||
|
||||
# Transmit Ports - pattern Generator Ports
|
||||
i_TXPRBSSEL=,
|
||||
i_TXPRBSSEL=0,
|
||||
|
||||
# Tx Configurable Driver Ports
|
||||
o_TXQPISENN=,
|
||||
o_TXQPISENP=
|
||||
#o_TXQPISENN=,
|
||||
#o_TXQPISENP=
|
||||
)
|
||||
|
||||
self.specials += \
|
||||
|
|
|
|||
Loading…
Reference in a new issue