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actorlib/spi: do not use MemoryPort

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Sebastien Bourdeauducq 2012-11-26 18:27:59 +01:00
parent 2418367c7a
commit fc85ca53ad
1 changed files with 8 additions and 14 deletions
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22
migen/actorlib/spi.py
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@ -94,15 +94,9 @@ class Collector(Actor):
return [self._reg_wa, self._reg_wc, self._reg_ra, self._reg_rd] return [self._reg_wa, self._reg_wc, self._reg_ra, self._reg_rd]
def get_fragment(self): def get_fragment(self):
wa = Signal(BV(bits_for(self._depth-1))) mem = Memory(self._dw, self._depth)
dummy = Signal(BV(self._dw)) wp = mem.get_port(write_capable=True)
wd = Signal(BV(self._dw)) rp = mem.get_port()
we = Signal()
wp = MemoryPort(wa, dummy, we, wd)
ra = Signal(BV(bits_for(self._depth-1)))
rd = Signal(BV(self._dw))
rp = MemoryPort(ra, rd)
mem = Memory(self._dw, self._depth, wp, rp)
comb = [ comb = [
If(self._reg_wc.field.r != 0, If(self._reg_wc.field.r != 0,
@ -110,17 +104,17 @@ class Collector(Actor):
If(self.endpoints["sink"].stb, If(self.endpoints["sink"].stb,
self._reg_wa.field.we.eq(1), self._reg_wa.field.we.eq(1),
self._reg_wc.field.we.eq(1), self._reg_wc.field.we.eq(1),
we.eq(1) wp.we.eq(1)
) )
), ),
self._reg_wa.field.w.eq(self._reg_wa.field.r + 1), self._reg_wa.field.w.eq(self._reg_wa.field.r + 1),
self._reg_wc.field.w.eq(self._reg_wc.field.r - 1), self._reg_wc.field.w.eq(self._reg_wc.field.r - 1),
wa.eq(self._reg_wa.field.r), wp.adr.eq(self._reg_wa.field.r),
wd.eq(Cat(*self.token("sink").flatten())), wp.dat_w.eq(Cat(*self.token("sink").flatten())),
ra.eq(self._reg_ra.field.r), rp.adr.eq(self._reg_ra.field.r),
self._reg_rd.field.w.eq(rd) self._reg_rd.field.w.eq(rp.dat_r)
] ]
return Fragment(comb, memories=[mem]) return Fragment(comb, memories=[mem])