litex_sim: add --gtkwave-savefile argument with example signals

litex/tools/litex_sim.py

@@ -23,6 +23,7 @@ from litex.soc.integration.builder import *
 from litex.soc.integration.soc import *
 from litex.soc.cores.bitbang import *
 from litex.soc.cores.cpu import CPUS
+from litex.build.sim import gtkwave as gtkw
 
 from litedram import modules as litedram_modules
 from litedram.modules import parse_spd_hexdump
@@ -326,6 +327,41 @@ class SimSoC(SoCCore):
 
 # Build --------------------------------------------------------------------------------------------
 
+def generate_gtkw_savefile(builder, vns, trace_fst):
+    dumpfile = os.path.join(builder.gateware_dir, "sim.{}".format("fst" if trace_fst else "vcd"))
+    savefile = os.path.join(builder.gateware_dir, "sim.gtkw")
+    soc = builder.soc
+
+    with gtkw.GTKWSave(vns, savefile=savefile, dumpfile=dumpfile) as save:
+        save.clocks()
+        save.fsm_states(soc)
+        save.add(soc.bus.slaves["main_ram"], mappers=[gtkw.wishbone_sorter(), gtkw.wishbone_colorer()])
+
+        if hasattr(soc, 'sdrphy'):
+            # all dfi signals
+            save.add(soc.sdrphy.dfi, mappers=[gtkw.dfi_sorter(), gtkw.dfi_in_phase_colorer()])
+
+            # each phase in separate group
+            with save.gtkw.group("dfi phaseX", closed=True):
+                for i, phase in enumerate(soc.sdrphy.dfi.phases):
+                    save.add(phase, group_name="dfi p{}".format(i), mappers=[
+                        gtkw.dfi_sorter(phases=False),
+                        gtkw.dfi_in_phase_colorer(),
+                    ])
+
+            # only dfi command/data signals
+            def dfi_group(name, suffixes):
+                save.add(soc.sdrphy.dfi, group_name=name, mappers=[
+                    gtkw.regex_filter(gtkw.suffixes2re(suffixes)),
+                    gtkw.dfi_sorter(),
+                    gtkw.dfi_per_phase_colorer(),
+                ])
+
+            dfi_group("dfi commands", ["cas_n", "ras_n", "we_n"])
+            dfi_group("dfi commands", ["wrdata"])
+            dfi_group("dfi commands", ["wrdata_mask"])
+            dfi_group("dfi commands", ["rddata"])
+
 def sim_args(parser):
     builder_args(parser)
     soc_sdram_args(parser)
@@ -351,6 +387,7 @@ def sim_args(parser):
     parser.add_argument("--trace-end",            default="-1",            help="Time to end tracing (ps)")
     parser.add_argument("--opt-level",            default="O3",            help="Compilation optimization level")
     parser.add_argument("--sim-debug",            action="store_true",     help="Add simulation debugging modules")
+    parser.add_argument("--gtkwave-savefile",     action="store_true",     help="Generate GTKWave savefile")
 
 def main():
     parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
@@ -433,6 +470,8 @@ def main():
         )
         if args.with_analyzer:
             soc.analyzer.export_csv(vns, "analyzer.csv")
+        if args.gtkwave_savefile:
+            generate_gtkw_savefile(builder, vns, args.trace_fst)
 
 if __name__ == "__main__":
     main()