etherbone: wishbone reads seems OK in simulation

liteeth/core/etherbone/record.py

@@ -124,10 +124,13 @@ class LiteEthEtherboneRecordSender(Module):
 			source.sop.eq(0),
 			source.eop.eq(wr_buffer.source.eop),
 			source.data.eq(wr_buffer.source.data),
-			If(source.stb & source.eop & source.ack,
+			If(source.stb & source.ack,
+				wr_buffer.source.ack.eq(1),
+				If(source.eop,
 					NextState("IDLE")
 				)
 			)
+		)
 
 # Note: for now only support 1 record per packet
 class LiteEthEtherboneRecord(Module):
@@ -143,10 +146,26 @@ class LiteEthEtherboneRecord(Module):
 			receiver.sink.data.eq(reverse_bytes(depacketizer.source.data)) # clarify this
 		]
 
+		last_ip_address = Signal(32) # XXX for test
+		last_src_port = Signal(16)   # XXX for test
+		last_dst_port = Signal(16)   # XXX for test
+
+		self.sync += [
+			If(sink.stb & sink.sop & sink.ack,
+				last_ip_address.eq(sink.ip_address),
+				last_src_port.eq(sink.src_port),
+				last_dst_port.eq(sink.dst_port)
+			)
+		]
+
 		self.submodules.sender = sender =  LiteEthEtherboneRecordSender()
 		self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
 		self.comb += [
 			Record.connect(sender.source, packetizer.sink),
 			packetizer.sink.data.eq(reverse_bytes(sender.source.data)), # clarify this
 			Record.connect(packetizer.source, source),
+			source.length.eq(sender.source.wcount*4 + 4),
+			source.ip_address.eq(last_ip_address),
+			source.src_port.eq(last_src_port),
+			source.dst_port.eq(last_dst_port)
 		]

liteeth/core/etherbone/wishbone.py

@@ -58,7 +58,8 @@ class LiteEthEtherboneWishboneMaster(Module):
 			wr_source.addr.eq(rd_sink.addr),
 			wr_source.count.eq(rd_sink.count),
 			wr_source.be.eq(rd_sink.be),
-			wr_source.data.eq(data.q),
+			#wr_source.data.eq(data.q),
+			wr_source.data.eq(0x12345678), # XXX
 			If(wr_source.stb & wr_source.ack,
 				rd_sink.ack.eq(1),
 				If(wr_source.eop,

liteeth/test/etherbone_tb.py

@@ -50,12 +50,21 @@ class TB(Module):
 		for i in range(100):
 			yield
 
+		test_probe = False
+		test_writes = False
+		test_reads = True
+
 		# test probe
-		#packet = etherbone.EtherbonePacket()
-		#packet.pf = 1
-		#self.etherbone_model.send(packet)
+		if test_probe:
+			packet = etherbone.EtherbonePacket()
+			packet.pf = 1
+			self.etherbone_model.send(packet)
+
+			for i in range(1024):
+				yield
 
 		# test writes
+		if test_writes:
 			writes = etherbone.EtherboneWrites(base_addr=0x1000)
 			for i in range(16):
 				writes.add(etherbone.EtherboneWrite(i))
@@ -75,10 +84,36 @@ class TB(Module):
 			packet = etherbone.EtherbonePacket()
 			packet.records = [record]
 			print(packet)
-
 			self.etherbone_model.send(packet)
 
+			for i in range(1024):
+				yield
 
+		# test reads
+		if test_reads:
+			reads = etherbone.EtherboneReads(base_ret_addr=0x2000)
+			for i in range(16):
+				reads.add(etherbone.EtherboneRead(i))
+			record = etherbone.EtherboneRecord()
+			record.writes = None
+			record.reads = reads
+			record.bca = 0
+			record.rca = 0
+			record.rff = 0
+			record.cyc = 0
+			record.wca = 0
+			record.wff = 0
+			record.byte_enable = 0
+			record.wcount = 0
+			record.rcount = 16
+
+			packet = etherbone.EtherbonePacket()
+			packet.records = [record]
+			print(packet)
+			self.etherbone_model.send(packet)
+
+			for i in range(1024):
+				yield
 
 if __name__ == "__main__":
-	run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)
+	run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)

liteeth/test/model/etherbone.py

@@ -143,8 +143,10 @@ class EtherboneRecord(Packet):
 		for k, v in sorted(etherbone_record_header.items()):
 			setattr(self, k, get_field_data(v, header))
 		self.writes = self.get_writes()
+		if self.writes is not None:
 			self.writes.decode()
 		self.reads = self.get_reads()
+		if self.reads is not None:
 			self.reads.decode()
 		self.encoded = False