Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

integration/soc: replace SDDataReader/SDDataWriter with DMAs.

This commit is contained in:
Florent Kermarrec 2020-06-24 12:23:35 +02:00
parent bc64e35480
commit fd4765e159
1 changed files with 16 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
litex/soc/integration/soc.py
View File

@ -18,6 +18,7 @@ from litex.soc.cores.spi import SPIMaster
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
from litex.soc.interconnect import csr_bus from litex.soc.interconnect import csr_bus
from litex.soc.interconnect import stream
from litex.soc.interconnect import wishbone from litex.soc.interconnect import wishbone
from litex.soc.interconnect import axi from litex.soc.interconnect import axi
@ -1252,7 +1253,7 @@ class LiteXSoC(SoC):
# Imports # Imports
from litesdcard.phy import SDPHY from litesdcard.phy import SDPHY
from litesdcard.core import SDCore from litesdcard.core import SDCore
from litesdcard.data import SDDataReader, SDDataWriter from litex.soc.cores.dma import WishboneDMAWriter, WishboneDMAReader
# Emulator / Pads # Emulator / Pads
if with_emulator: if with_emulator:
@ -1282,28 +1283,22 @@ class LiteXSoC(SoC):
self.add_csr("sdcore") self.add_csr("sdcore")
# SD Card Data Reader # SD Card Data Reader
sdread_mem = Memory(32, 512//4) sdreader_bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
sdread_sram = FullMemoryWE()(wishbone.SRAM(sdread_mem, read_only=True)) self.submodules.sdreader = WishboneDMAWriter(sdreader_bus, with_csr=True, endianness=self.cpu.endianness)
self.submodules += sdread_sram self.bus.add_master("sdreader", master=sdreader_bus)
self.bus.add_slave("sdread", sdread_sram.bus, SoCRegion(size=512, cached=False)) self.add_csr("sdreader")
self.submodules.sdreader_fifo = stream.SyncFIFO([("data", self.bus.data_width)], 512//(self.bus.data_width//8))
sdread_port = sdread_sram.mem.get_port(write_capable=True); self.comb += self.sdcore.source.connect(self.sdreader_fifo.sink)
self.specials += sdread_port self.comb += self.sdreader_fifo.source.connect(self.sdreader.sink)
self.submodules.sddatareader = SDDataReader(port=sdread_port, endianness=self.cpu.endianness)
self.add_csr("sddatareader")
self.comb += self.sdcore.source.connect(self.sddatareader.sink)
# SD Card Data Writer # SD Card Data Writer
sdwrite_mem = Memory(32, 512//4) sdwriter_bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
sdwrite_sram = FullMemoryWE()(wishbone.SRAM(sdwrite_mem, read_only=False)) self.submodules.sdwriter = WishboneDMAReader(sdwriter_bus, with_csr=True, endianness=self.cpu.endianness)
self.submodules += sdwrite_sram self.bus.add_master("sdwriter", master=sdwriter_bus)
self.bus.add_slave("sdwrite", sdwrite_sram.bus, SoCRegion(size=512, cached=False)) self.add_csr("sdwriter")
self.submodules.sdwriter_fifo = stream.SyncFIFO([("data", self.bus.data_width)], 512//(self.bus.data_width//8))
sdwrite_port = sdwrite_sram.mem.get_port(write_capable=False, async_read=True, mode=READ_FIRST); self.comb += self.sdwriter.source.connect(self.sdwriter_fifo.sink)
self.specials += sdwrite_port self.comb += self.sdwriter_fifo.source.connect(self.sdcore.sink)
self.submodules.sddatawriter = SDDataWriter(port=sdwrite_port, endianness=self.cpu.endianness)
self.add_csr("sddatawriter")
self.comb += self.sddatawriter.source.connect(self.sdcore.sink),
# Timing constraints # Timing constraints
if not with_emulator: if not with_emulator: