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utils/litex_sim: fix main_ram_size

This commit is contained in:
Florent Kermarrec 2019-03-16 21:25:02 +01:00
parent 3f386dad7d
commit fd7ed6c1ec
1 changed files with 1 additions and 1 deletions
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2
litex/utils/litex_sim.py
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@ -224,7 +224,7 @@ def main():
if args.rom_init: if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness) soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
if not args.with_sdram: if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x1000000 # 256 MB soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None: if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness) soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness)
else: else: