build/efinix/efinity: Add resolve_iface_signal_names method to automatically resolve ClockSignal/Signal names passed in the blocks.

Allow the Migen/LiteX build elaboration to resolve signal names and just use it in blocks to avoid name_override workaround.

litex/build/efinix/efinity.py

@@ -222,9 +222,33 @@ class EfinityToolchain(GenericToolchain):
 
         return "\n".join(conf)
 
+    def resolve_iface_signal_names(self):
+        # Iterate over each block
+        for block in self.platform.toolchain.ifacewriter.blocks:
+
+            # Iterate over each key-value pair in the block
+            for key, value in block.items():
+
+                # Only process specific keys, skip others.
+                if key not in ["name", "in_clk_pin", "out_clk_pin"]:
+                    continue
+
+                # If the value is a ClockSignal, resolve its name
+                if isinstance(value, ClockSignal):
+                    clock_domain = value.cd
+                    signal_name = self._vns.get_name(self._vns.clock_domains[clock_domain].clk)
+                    block[key] = signal_name  # Replace with the resolved name
+
+                # If the value is a Signal, directly resolve its name
+                elif isinstance(value, Signal):
+                    signal_name = self._vns.get_name(value)
+                    block[key] = signal_name  # Replace with the resolved name
+
     def build_io_constraints(self):
         pythonpath = ""
 
+        self.resolve_iface_signal_names()
+
         header = self.ifacewriter.header(self._build_name, self.platform.device)
         gen    = self.ifacewriter.generate(self.platform.device)
         #TODO  : move this to ifacewriter